TI486 Microprocessor - Al Kossow's Bitsavers

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8MI Handler Example COMMENT A The TX486 SMM support for X/O being interrupted provides information that per.mits the restarting of the X/O instruction without investigating the actual code where the instruction is located. Many things can be done at this point beyond turning on a powered down peripheral. The CPU clock could now be speeded up in anticipation of heavy CPU processing requirements, timers could be reset, etc. i** Restart the interrupted instruction mov mov mov itest for REP instruction bt adc test jnz eax,dword ptr [SMEND+SMI_PREVIOUSIP] dword ptr [SMEND+SMI_NEXTIP],eax al,byte ptr cs: [SMEND+SMI_BITS] al,2 ecx,O al,l shl 1 irep instruction? i (result to Carry) iif so, increment ecx itest bit 1 to see iif an OUTS or INS COMMENT A ** A port read (INx) instruction caused the chip set to generate an SMI instruction. Restore EDI saved by SMI microcode. mov jmp out_instr: edi, dword ptr cs: [SMEND+SMI_EDIESI] commonl COMMENT A ** A port write (OUTx) instruction caused the chip set to generate an SMI instruction. Restore ESI saved by SMI microcode. mov commonl: jmp done esi, dword ptr cs: [SMEND+SMI_EDIESI] A-19
8MI Handler Example COMMENT A This handler turned off the current to the cpu. Before it did, the handler set a bit in main memory or battery backed-up CMOS indicating that this event happened. At reset, BIOS will deter.mine that this was the case and "jump" into the SMI handler. SMI handler will then restore the entire state/context of the cpu prior to current being removed. The bit in main memory would also be cleared indicating that the SMI handler had removed current. mov ax, a mov ds, ax mov [485], a mov ax, cs mov ds, ax point to bottom segment ds segment is now in main memory clear BIOS flag in main memory restore ds to SMM area {Restore Complete CPU State} eax ebx ecx edx edi esi ebp esp cs ds ss es fs gs ldtr gdtr idtr tr eflags cra cr2 cr3 dra drl dr2 dr3 dr6 dr7 ccra ccrl ccr2 iuse iuse iuse iuse iuse iuse rsdc rsdc rsdc rsdc rsdc rsdc Save the configuration registers with index C3h through FFh A-20 <strong>TI486</strong> 8MM Programmer's Guide
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
Page 254 and 255: -....J N (J.) Table 7-17. Instructi
Page 256 and 257: I I i I i Table 7-17. Instructions,
Page 258 and 259: ...... ...... '" Table 7-17. Instru
Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 286 and 287: 8MI Handler Example arrl arr2 arr3
Page 288 and 289: .MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291: Testing/Debugging SMM Code sgdt COM
Page 292 and 293: Testing/Debugging SMM Code i*******
Page 294 and 295: TI486 Power Management Features A.7
Page 296 and 297: Detection of Tl486 CPU A.9 Detectio
Page 298 and 299: Detection of SMM Capable Version A.
Page 300 and 301: i**********************************
Page 302 and 303: A.11 SMM Feature Comparison SMM Fea
Page 304 and 305: SMM Instruction Macros COMMENT A Co
Page 306 and 307: SMM Instruction Macros SMM Instruct
Page 308 and 309: A.14 Format of Data Used by SVDC/RS
Page 310 and 311: Altering SMM Code Limits A.1S Alter
Page 312 and 313: SMM Errata A.16 SMM Errata The foll
Page 314 and 315: Appendix B TI486 Cache Flush B.1 Ge
Page 316 and 317: Appendix C TI486 BIOS Modification
Page 318 and 319: Introduction Some example assembler
Page 320 and 321: Appendix D Ordering Information 0.1
Page 322: ~TEXAS INSTRUMENTS Printed in U.S.A
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