TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
4.2.10 Coprocessor Interface
The coprocessor interface consists of the data bus, address bus, bus cycle
definition signals, and the coprocessor interface signals (BUSY, ERROR and
PEREQ). The TI486DLC/E automatically accesses dedicated coprocessor
1/0 address 8000 00F8h and 80 OOFCh to transfer opcodes and operands to
or from the coprocessor whenever a coprocessor instruction is decoded.
Coprocessor cycles can be either read or write and can be either non-pipelined
or pipelined. Coprocessor cycles must be terminated by READY and, as with
any other bus cycle, can be terminated as early as the second bus state of the
cycle.
BUSY, ERROR, and PEREQ are asynchronous level-sensitive inputs used to
synchronize CPU and coprocessor operation. All three signals are sampled
at the beginning of phase 1 and must meet specified setup and hold times to
be recognized at a given CLK2 edge.
4.2.11 SMM Interface
4.2.11.1 SMI Handshake
8ystem Management Mode (SMM) uses two TI486DLC/E pins, SMI and
SMADS. the bidirectional SMI pin is a non-maskable interrupt that is higher
priority than the NMI input. 8MI must be active for at least four CLK2 periods
to be recognized by the TI486DLC/E. Once the TI486DLC/E recognizes the
active SMI input, the CPU drives the SMI pin low for the duration of the SMI
service routine.
The SMADS pin outputs the SMM Address Strobe that indicates a SMM
memory bus cycle is in progress and a valid SMM address is on the address
bus. The SMADS functional timing, output delay times and float delay times
are identical to the main memory address strobe (ADS) timing.
The functional timing for SMI interrupt is shown in Figure 4-25. Five significant
events take place during a TI486DLC/E SMI handshake:
1) The 8MI input pin is driven active (low) by the system logic.
2) The CPU samples SMI active on the rising edge of CLK2 phase 1.
3) Four CLK2s after sampling the 8MI active, the CPU switches the SMI pin
to an output and drives SMllow.
4) Following execution of the R8M instruction, the CPU drives the 8MI pin
high for two CLK2s indicating completion of the 8MI service routine.
5) The CPU stops driving the 8MI pin high and switches the SMI pin to an
input in preparation for the next SMI interrupt. The system logic is
responsible for maintaining the 8MI pin at an inactive (high) level after the
pin has been changed to an input.
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