TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Initiating and Maintaining Non-Pipelined Cycles
The bus states and transitions for non-pipelined addressing are illustrated in
Figure 4-7. The bus transitions between four possible states: T1, T2, Ti, and
Th. Active bus cycles consist of T1 and T2 states, with T2 being repeated for
wait states. Bus cycles always begin with a single T1 state. T1 is always
followed by a T2 state. If a bus cycle is not acknowledged during a given T2
and NA is inactive, T2 is repeated resulting in a wait state. When a cycle is
acknowledged during T2, the following state is T1 of the next bus cycle if a bus
request is pending internally. If no internal bus request is pending, the Ti state
is entered. If the HOLD input is asserted and the TI486DLC/E is ready to enter
the hold acknowledge state, the Th state is entered.
Figure 4-7. Non-Pipelined Bus States
HOLD Asserted
HOLD Negated
No Request
HOLD Asserted
READY Asserted
HOLD Asserted
READY Asserted
HOLD Negated
No Request
Request Pending
HOLD Negated
READY Asserted
HOLD Negated
Request Pending
Bus States:
T1 - First clock of a non-pipelined bus cycle