TI486 Microprocessor - Al Kossow's Bitsavers

Register Set
Table 2-14. TR6 and TR7 Bit Definitions
REGISTER
NAME
BIT
POSITION
DESCRIPTION
TR6 31-12 Linear address.
TLB lookup: The TLB is interrogated per this address. If one and only one match occurs in the
TLB, the rest of the fields in TR6 and TR7 are updated per the matching TLB entry.
TLB write: A TLB entry is allocated to this linear address.
11 Valid bit (V).
TLB lookup: Always set to 1.
TLB write: If set, indicates that the TLB entry contains valid data. If clear, target entry is
invalidated.
10-9 Dirty attribute bit and its complement (D, D). (Refer to Table 2-15).
8-7 User/supervisor attribute bit and its complement (U, U). (Refer to Table 2-15).
6-5 Read/write attribute bit and its complement (R, R). (Refer to Table 2-15).
0 Command bit (C).
If=O: TLB write.
If=1: TLB lookup.
TR7 31-12 Physical address.
TLB lookup: data field from the TLB.
TLB write: data field written into the TLB.
11 Page-level cache disable bit (PCD). Corresponds to the PCD bit of a page table entry.
10 Page-level cache write-through bit (PWT). Corresponds to the PWT bit of a page table entry.
9-7 LRU bits.
TLB lookup: LRU bits associated with the TLB entry prior to the TLB lookup.
TLB write: ignored.
4 PL bit.
TLB lookup: If=1, read hit occurred. If=O, read miss occurred.
TLB write: If=1, REP field is used to select the set. If=O, the pseudo-LRU replacement
algorithm is used to select the set.
3-2 Set selection (REP).
TLB lookup: If PL=1, set in which the tag was found. If PL=O, undefined data.
TLB write: If PL=1 , selects one of the four sets for replacement. If PL=O, ignored.
Table 2-15. TR6 Attribute Bit Pairs
BIT (B) BIT COMPLEMENT EFFECT ON EFFECT ON
(8) TLB LOOKUP TLBWRITE
0 0 Do not match Undefined
0 1 Match if the bit is 0 Clear the bit
1 0 Match if the bit is 1 Set the bit
1 1 Match is the bit is 1 or 0 Undefined
2-35