TI486 Microprocessor - Al Kossow's Bitsavers

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--- --;.J -L 01 Table 7-17. Instructions, Opcodes, Flags, and Clock Summary (Continued) FLAGS REAL MODE CLOCKS INSTRUCTION OPCODE REGI REG! 0 D I T S Z A P C CACHE CACHE CACHE F F F F F F F F F MISS HIT HIT PROTECTED MODE CLOCKS NOTES CACHE READ PROTECTED MISS MODE MODE BSR Scan Bit Reverse u u u u u m u u u 1 2 Register/Memory, Register OF BC[mod reg rIm] 517+n 9+n 5/7+n 9+n BSWAP Byte Swap OF C[1 reg] u u u u u u u u u 4 4 BT Test Bit u u u u u u u u m 1 2 Register/Memory, Immediate OF BA[mod 100 r/m]t 3/4 5 3/4 5 Register/Memory, Register OF A3[mod reg rIm] 3/6 7 3/6 7 BTC Test Bit and Complement u u u u u u u u m 1 2 Register/Memory, Immediate OF BA[mod 111 r/m]t 4/5 6 4/5 6 Register/Memory, Register OF BB[mod reg rIm] 5/8 9 5/8 9 BTR Test Bit and Reset u u u u u u u u m 1 2 Register/Memory, Immediate OF BA[mod 110 r/m]t 4/5 6 4/5 6 Register/Memory, Register OF B3[mod reg rIm] 5/8 9 5/8 9 BTS Test Bit and Set u u u u u u u u m 1 2 Register/Memory OF BA[mod 101 rIm] 3/5 6 3/5 6 Register (short form) OF ~~[mod reg rIm] 4/7 8 417 8 -------- ~-- - t = immediate data + = 8-bit displacement § = 16-bit displacement 11 = 32-bit displacement m = Flag modified u = Flag unchanged Notes: 1) Exception 13 fault (general protection) will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum CS, OS, ES, FS, or GS segment limit (FFFFh). Exception 12 fault (stack segment limit violation or not present) will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum SS limit. 2) Exception 13 fault will occur if the memory operand in CS, OS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit is violated, an exception 12 occurs. 3) This is a Protected Mode instruction. Attempted execution in Real Mode will result in exception 6 (invalid opcode). 4) An exception may occur, depending on the value of the operand. 5) LOCK is asserted during descriptor table accesses. 6) <strong>Al</strong>l segment descriptor accesses in the GOT or LOT made by this instruction will automatically assert LOCK to maintain descriptor integrity in multiprocessor systems. 7) JMP, CALL, INT, RET, and IRET instructions referring to another code segment will cause an exception 13, if an applicable privilege rule is violated. 8) The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault will occur. Q o ~ ~ ~ I ~
~ ....L 0) Table 7-17. Instructions, Opcodes, Flags, and Clock Summary (Continued) INSTRUCTION OPCODE FLAGS 0 D I T S Z F F F F F F CALL Subroutine Call u u u u u u Direct within Segment E8~ RegisterlMemory Indirect within Segment FF [mod 010 rIm] A F u P F u C F u REAL MODE CLOCKS REGI CACHE CACHE MISS HIT 7 8/9 10 PROTECTED MODE CLOCKS REGI CACHE CACHE MISS HIT 7 8/9 10 READ MODE 1 NOTES PROTECTED MODE 2,6,7,8 () 0- ~ ~ ~ C/) § :3 III ~ Direct Intersegment Call Gate to Same Privilege Call Gate to Different Privilege No P Call Gate to Different Privilege Ps 16-Bit Task to 16-bit TSS 16-Bit Task to 32-bit TSS 16-Bit Task to V86 Task 32-Bit Task to 16-bit TSS 32-Bit Task to 32-bit TSS 32-Bit Task to V86 Task 9A [unsigned full offset, selector] 12 30 41 49 83 97 81+4x 95+4x 262 263 293 317 179 206 238 258 296 340 182 229 Indirect Intersegment Call Gate to Same Privilege Call Gate to Different Privilege No P Call Gate to Different Privilege Ps 16-Bit Task to 16-bit TSS 16-Bit Task to 32-bit TSS 16-Bit Task to V86 Task 32-Bit Task to 16-bit TSS 32-Bit Task to 32-bit TSS 32-Bit Task to V86 Task FF [mod 011 rIm] 14 17 14 34 43 51 85 99 86+4x 100+4x 267 268 298 322 181 211 243 263 301 345 184 230 P = Parameters CBW Convert Byte to Word 98 u u u u u u u u u 3 3 CDa Convert Doubleword to Quadword 99 u u u u u u u u u 1 1 CLC Clear Carry Flag F8 u u u u u u u u 0 1 1 CLD Clear Direction Flag FC u 0 u u u u u u u 1 1 CLI Clear Interrupt Flag FA u u 0 u u u u u u 7 7 9 CLTS Clear Task Switched Flag OF06 u u u u u u u u u 5 5 10 11 ~ ~ ~ 5' :::J ~ ..... CMC Complement the Carry Flag F5 u u u u u u CMP Compare Integers m Register to Register 3 [10dw] [11 reg rIm] u u u m m Register to Memory 3 [101 w] [mod reg rIm] Memory to Register 3 [100w] [mod reg rIm] Immediate to RegisterlMemory 8 [OOsw] [mod 111 r/m]t Immediate to Accumulator 3 [110w]t u m u m 1 m m 1 3 5 3 5 1/3 5 1 1 1 3 5 3 5 1/3 5 1 1 2
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
Page 196 and 197: Functional Timing Stopping the Inpu
Page 198 and 199: Electrical Specifications 5-1
Page 200 and 201: Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
Page 210 and 211: AC Characteristics Table 5-9. AC Ch
Page 212 and 213: AC Characteristics Table 5-11. AC C
Page 214 and 215: ____ AC Characteristics 5.5.3 RESET
Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
Page 254 and 255: -....J N (J.) Table 7-17. Instructi
Page 256 and 257: I I i I i Table 7-17. Instructions,
Page 258 and 259: ...... ...... '" Table 7-17. Instru
Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 284 and 285: 8MI Handler Example COMMENT A The T
Page 286 and 287: 8MI Handler Example arrl arr2 arr3
Page 288 and 289: .MODEL SMALL . STACK .386P INCLUDE
Page 290 and 291: Testing/Debugging SMM Code sgdt COM
Page 292 and 293: Testing/Debugging SMM Code i*******
Page 294 and 295: TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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