TI486 Microprocessor - Al Kossow's Bitsavers

Register Set
Cache Test Registers
Table 2-16. TR3-TR5 Bit Definitions
REGISTER
NAME
The TI486 on-chip cache can be configured either as a direct-mapped (256
entries) or as a two-way set associative memory (128 entries per set). Each
entry consists of a 23-bit tag, 32-bit data field, four valid bits, and an LRU bit.
The 23-bit tag represents the high-order 23 bits of the physical address. The
32-bit data represents the four bytes of data currently in memory at the
physical address represented by the tag. The four valid bits indicate which of
the four data bytes contain valid data. The LRU bit is accessed only when the
cache is configured as two-way set associative and indicates which of the two
sets was most recently accessed.
The TI486 contains three test registers that allow testing of its internal cache.
Using these registers, cache test writes and reads may be performed. Cache
test writes cause the data in TR3 to be written to the selected set and entry in
the cache. Cache test reads allow inspection of the data, valid bits and the LRU
bit for the cache entry. For data to be written to the allocated entry, the valid
bits for the entry must be set prior to the write of the data. Bit definitions for the
cache test registers are shown in Table 2-16.
BIT
POSITION
DESCRIPTION
TR3 31-10 Cache data.
Cache read: data accessed from the cache.
Cache write: to be written into the cache.
TR4 31-9 Tag address.
Cache read: tag address from which data is read.
Cache write: data written into the tag address of the selected line.
7 LRU
Cache read: the LRU bit associated with the cache line.
Cache write: ignored.
6-3 Valid bits
Cache reads: four valid bits for the accessed line, (one bit per byte).
Cache writes: valid bits written into the line.
TR5 10-4 Line selection. Selects one of 128 lines.
2 Set selection
If=O: set 0 is selected
If=1: set 1 is selected
1-0 Control bits. These bits control reading or writing the cache.
If=OO: Ignored
If=01: Cache write
If=10: Cache read
If=11: Cache flush (marks all entries as invalid).
2-36 Programming Interface