TI486 Microprocessor - Al Kossow's Bitsavers

Overview
Table 3-2. Terminal Functions
NAME
PIN
NO.
I/O
DESCRIPTION
A1 18
A2 51
A3 52
A4 53
A5 54
A6 55
A7 56 Address Bus (active high). The address bus (A23-A 1) signals are 3-state outputs that
A8 58 provide addresses for physical memory and I/O ports. All address lines can be used for
A9 59 addressing physical memory allowing a 16 MByte address space (00 OOOOh to FF
A10 60 FFFFh). During I/O port accesses, A23-A16 are driven low (except for coprocessor
A11 61 accesses). This permits a 64 KByte I/O address space (00 OOOOh to 00 FFFFh).
A12 62 O/Z
A13 64 During all coprocessor I/O access address lines A22-A 16 are driven low and A23 is
A14 65 driven high. This allows A23 to be used by external logic to generate a coprocessor select
A15 66 signal. Coprocessor command transfers occur with address 80 00F8h and coprocessor
A16 70 data transfers occur with addresses 80 OOFCh and 90 OOFEh. A23-A 1 float while the
A17 72 CPU is in a hold acknowledge or float state.
A18 73
A19 74
A20 75
A21 76
A22 79
A23 80
ADS 16 O/Z Address Strobe (active low). This is a 3-state output that indicates the TI486 has driven
a valid address (A23-A 1, BHE, BLE) and bus cycle definition (M/IO), DIG, W/R) on the
appropriate TI486SLC/E output pins. During non-pipelined bus cycles, ADS is active for
the first clock of the bus cycle. During address pipelining, ADS is asserted during the
previous bus cycle and remains asserted until READY is returned for that cycle. ADS
floats while the TI486SLC/E is in a hold acknowledge or float state.
A20M 31 I Address Bit 20 Mask (active low). This input causes the TI486SLC/E to mask (force
low) physical address bit 20 when driving the external address bus or performing an
internal cache access. When the processor is in real mode, asserting A20M emUlates
the 1 MByte address wrap around that occurs on the 8086. The A20 signal is never
masked when paging is enabled regardless of the state of the A20M input. The A20M
input is ignored following reset and can be enabled using the A20M bit in the CCRO
configuration register.
A20M is internally connected to a pullup resistor to prevent it from floating active when
left unconnected.
BHE 19 O/Z Byte Enables (active low). Byte Low Enable (BLE) and Syte High Enable (SHE) are
SLE 17 3-state outputs that indicate which byte(s) of the 16-bit data bus will be selected for data
transfer during the current bus cycle. BLE selects the low byte (D7-DO) and SHE selects
the high byte (D15-D8).
When BHE and SLE are asserted, both bytes (all 16 bits) of the data bus are selected.
SLE and SHE float while the CPU is in a hold acknowledge or float state.
BHE = SLE = 1 never occurs during a bus cycle.
3-6 TI486SLCIE Bus Interface