TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
4.2.9 Hold Acknowledge State
The hold acknowledge state provides the mechanism for an external device
in a TI486DLC/E system to acquire the TI486DLC/E system bus while the
TI486DLC/E is held in an inactive bus state. This allows external bus masters
to take control of the TI486DLC/E bus and directly access system hardware
in a shared manner with the TI486DLC/E. The TI486DLC/E continues to
execute instructions out of the cache (if enabled) until a system bus cycle is
required.
The hold acknowledge state (Th) is entered in response to assertion of the
HOLD input. in the hold acknowledge state, the TI486DLC/E microprocessor
floats all output and bidirectional signals, except for HLDA and SUSPA. HLDA
is asserted as long as the TI486DLC/E CPU remains in the hold acknowledge
state and all inputs except HOLD, FLUSH, SUSP and RESET are ignored.
Th may be entered directly from a bus idle state, as in Figure 4-22, or after the
completion of the current physical bus cycle if the LOCK signal is not asserted,
as in Figure 4-23 and Figure 4-24. The CPU samples the HOLD input on the
rising edge of CLK2 corresponding to the beginning of phase 1 of internal
processor clock. HOLD must meet specified setup and hold times to be
recognized at a given CLK2edge.
The hold acknowledge state is exited in response to the HOLD input being
negated. The next bus start is an idle state (Ti) if no bus request is pending,
as in Figure 4-22. If a bus request is internally pending, as in Figure 4-23 and
Figure 4-24, the next bus state is T1. Th is also exited in response to RESET
being asserted. If HOLD remains asserted when RESET goes inactive, the
TI486DLC/E enters the hold acknowledge state before performing any bus
cycles provided HOLD is still asserted when the CPU is ready to perform its
first bus cycle.
If a rising edge occurs on the edge-triggered NMI input while in Th state, the
event is remembered as a non-maskable interrupt 2 and is serviced when the
state is exited.
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