TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
3.2.8 Hold Acknowledge State
The hold acknowledge state provides the mechanism for an external device
in a TI486SLC/E system to acquire the TI486SLC/E system bus while the
TI486SLC/E is held in an inactive bus state. This allows external bus masters
to take control of the TI486SLC/E bus and directly access system hardware
in a shared manner with the TI486SLC/E. The TI486SLC/E continues to
execute instructions out of the cache (if enabled) until a system bus cycle is
required.
The hold acknowledge state (Th) is entered in response to assertion of the
HOLD input. in the hold acknowledge state, the TI486SLC/E microprocessor
floats all output and bidirectional signals, except for HLDA and SUSPA. HLDA
is asserted as long as the TI486SLC/E CPU remains in the hold acknowledge
state and all inputs except HOLD, FLUSH, FLT, SUSP and RESET are
ignored.
State Th may be entered directly from a bus idle state, as in Figure 3-19, or
after the completion of the current physical bus cycle if the LOCK signal is not
asserted, as in Figure 3-20 and Figure 3-21. The CPU samples the HOLD
input on the rising edge of CLK2 corresponding to the beginning of phase 1
of internal processor clock. HOLD must meet specified setup and hold times
to be recognized at a given CLK2 edge.
The hold acknowledge state is exited in response to the HOLD input being
negated. The next bus start is an idle state (Ti) if no bus request is pending,
as in Figure 3-19. If a bus request is internally pending, as in Figure 3-20 and
Figure 3-21, the next bus state is T1. State Th is also exited in response to
RESET being asserted. If HOLD remains asserted when RESET goes
inactive, the TI486SLC/E enters the hold acknowledge state before
performing any bus cycles provided HOLD is still asserted when the CPU is
ready to perform its first bus cycle.
If a rising edge occurs on the edge-triggered NMI input while in state Th, the
event is remembered as a non-maskable interrupt 2 and is serviced when the
state is exited.
3-38
TI486SLCIE Bus Interface