TI486 Microprocessor - Al Kossow's Bitsavers

Overview
4.1 Overview
The following sections describe the TI486DLC/E input and output signals. The
discussion of these signals is arranged by functional groups as shown in
Figure 4-1. Table 4-1 gives a brief description of each of the TI486DLC/E
signals.
Figure 4-1. TI486DLCIE Functional Signal Groupings
2x Clock
----. CLK2
TI486DLC/E
INTR
Reset ----. RESET NMI } Interrupt
Control
Address { A31-A2 SMI
Bus
BE3-BEO
KEN } Internal
Cache
Data
D31-DO FLUSH Interface
Bus
Bus
Cycle
Definition
{
WiR
A20M
DIG
MilO
PEREQ
Address Bit
20 Mask
LOCK BUSY } Coprocessor
Interface
----. BS16 ERROR
----. NA HOLD
Bus
Cycle READY HLDA
Control
ADS
SUSP
SMADS
SUSPA
} Bus
Arbitration
}
Power
Management
4-4 T1486DLCIE Bus Interface