TI486 Microprocessor - Al Kossow's Bitsavers

Overview
4.1.1 Bus Cycle Definition
Table 4-7. Bus Cycle Types
The bus cycle definition (MilO, D/C, W IR, LOCK) signals consist of four 3-state
outputs that define the type of bus cycle operation being performed. Table 4-7
defines the bus cycles for the possible states of these signals. MilO, DIG and
w/f5. are the primary bus cycle definition signals and are driven valid as ADS
(Address Strobe) becomes active. During non-pipelined cycles, the LOCK
output is driven valid along with MilO, D/C and W/R. During pipelined
addressing, LOCK is driven at the beginning of the bus cycle, which is after
ADS becomes active for that cycle. The bus cycle definition signals are active
low and float while the TI486DLC/E is in a hold acknowledge or float state.
MilO DIC W/R LOCK BUS CYCLE TYPE
0 0 0 0 Interrupt acknowledge
0 0 0 1 -
0 0 1 X -
0 1 X 0 -
0 1 0 1 I/O data read
0 1 1 1 I/O data write
1 0 X 0 -
1 0 0 1 Memory code read
1 0 1 1
Halt: A31-A2=Oh, BE3-BEO=1011
Shutdown: A31-A2=Oh, BE3-BEO=1110
1 1 0 0 Locked memory data read
1 1 0 1 Memory data read
1 1 1 0 Locked memory data write
1 1 1 1 Memory data write
X = don't care
- = does not occur
4-14 T1486DLCIE Bus Interface