TI486 Microprocessor - Al Kossow's Bitsavers

Appendix C
TI486 BIOS Modification Guide
C.1 Introduction
In order to reap full benefit from the TI486 microprocessors, the system BIOS
should be modified to support the internal registers that control the on-chip
cache and other extra features. This Appendix serves as a guide to some of
the changes that need to be considered, and includes sample assembler code
for controlling the cache.
There are three main areas of consideration that will be discussed in relation
to the internal cache registers:
• Power-on and hard reset
• Protected-mode to real-mode switching
• Soft reseVCTRL-ALT-DEL
In each case, the state of the CPU cache registers and when and how to
change their values must be known.
C.1.1
Power-On and Hard Reset
In these two cases, the system will be booted into the operating system. Due
to the reset line to the CPU going active, the internal cache will be disabled,
making the CPU act much like a 386. At some point the cache must be turned
on before the as is booted. A convenient time to turn on the cache may be
during final chip set initialization, understanding that the cache should remain
off during memory sizing. Many BlOSs provide the user an option to disable
the system cache using the setup screen. As most user cache control options
are stored in non-volatile RAM, the flag responses, and potentially other flags,
should be checked before turning the cache on.
C-1