TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Once a pipelined bus cycle is in progress, pipelined timing is maintained for
the next cycle by asserting NA and detecting that the TI486DLC/E
microprocessor enters T2P during the current bus cycle. The current bus cycle
must end in state T2P for pipelining to be maintained in the next cycle. T2P is
identified by the assertion of ADS. Figure 4-10 and Figure 4-11 each show
pipelining ending after Cycle 4. This occurred because the TI486DLC/E CPU
did not have an internal bus request prior to the acknowledgment of Cycle 4.
Figure 4-11. Transitioning to Pipelined Address During Burst of Bus Cycles
CLK2
Cycle 1 I Cycle 2 Cycle 3 I Cycle 4 I Idle I Non-Pipelined I Non-Pipelined I Pipelined I Pipelined I Idle
____ ~.~~r--(-W-rit-e)----.1~4------(R-e-ad-)------•• ~---(-W-rit-e)--~.~~.---(-Re-a-d)--4.~14.---~
I I I 1- I I
I Ti I T1 T2 I T1 T2P I T1 P : T2P I T1 P I Ti
A31-A2, I I
BE3-BEO, ~
M/IO,O/C~
WiR !~~'''''--i-l '--____ +_'
READY~
LOCK~ V~lid1
~I
I I ~~I----~~
031-00 ~---r-< Out 1
I I I
Note:
Following any idle bus state (Ti), addresses are non-pipelined bus cycles, NA is sampled only during wait states.
Therefore, to begin address pipelining during a group of non-pipelined bus cycles requires a non-pipelined cycle with at
least one wait state (Cycle 2 above).
The complete bus state transition diagram, including operation with pipelined
address is given in Figure 3-12. This is a superset of the diagram for
non-pipelined address. The three additional bus states for pipelined address
are shaded.
4-29