TI486 Microprocessor - Al Kossow's Bitsavers

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Instruction Fields 7.2 Instruction Fields The general instruction format shows the larger fields that make up an instruction. Certain instructions have smaller encoding fields that vary according to the class of operation. These fields define information such as the direction of the operation, the size of the displacements, register encoding and sign extension. <strong>Al</strong>l the fields are described in Table 7-1 and the subsequent paragraphs provide greater detail. Table 7-1. Instruction Fields FIELD NAME Prefix Opcode w d s reg mod rim ss index base sreg2 sreg3 eee Address displacement Immediate data DESCRIPTION NUMBER OF BITS Specifies segment register override, address and operand size, repeat elements in string instruction, LOCK assertion. 8 per byte Identifies instruction operation. 1 or 2 bytes Specifies if data is byte or full size (full size is either 16 or 32 bits). 1 Specifies direction of data operation. 1 Specifies if an immediate data field must be sign-extended. 1 General register specifier. 3 Address mode specifier. 2 for mod; 3 for rim Scale factor for scaled index address mode. 2 General register to be used as index register. 3 General register to be used as base register. 2 Segment register for CS, SS, DS, and ES. 2 Segment register for CS, SS, DS, ES, FS, and GS. 3 Control, debug and test register specifier. 3 Address displacement operand. 1 , 2 or 4 bytes Immediate data operand. 1 , 2 or 4 bytes 7.2.1 Prefixes Prefix bytes can be placed in front of any instruction. The prefix modifies the operation of the immediately following instruction only. When more than one prefix is used, the order is not important. There are five types of prefixes as follows: 1) Segment override explicitly specifies which segment register an instruction will use. 2) Address size switches between 16- and 32-bit addressing. Selects the inverse of the default. 3) Operand size switches between 16- and 32-bit addressing. Selects the inverse of the default. 4) Repeat is used with a string instruction which causes the instruction to be repeated for each element of the string. 5) Lock is used to assert the hardware LOCK signal during execution of the instruction. 7-5
Instruction Fields Table 7-2. Instruction Prefix Summary 7.2.2 Opcode Field Table 7-2 lists the encodings for each of the available prefix bytes. The operand size and address size prefixes allow the individual overriding of the default value for operand size and effective address size. The presence of these prefixes select the opposite (non-default) operand size and/or effective address size as the case may be. PREFIX ENCODING DESCRIPTION ES: 26h Override segment default, use ES for memory operand. CS: 2Eh Override segment default, use CS for memory operand. SS: 36h Override segment default, use SS for memory operand. DS: 3Eh Override segment default, use DS for memory operand. FS: 64h Override segment default, use FS for memory operand. GS: 65h Override segment default, use GS for memory operand. Operand size 66h Make operand size attribute the inverse of the default. Address size 67h Make address size attribute the inverse of the default. LOCK FOh Assert LOCK hardware signal. REPNE F2h Repeat the following string instruction. REP/REPE F3h Repeat the following string instruction. The opcode field is either one or two bytes in length and specifies the operation to be performed by the instruction. Some operations have more than one opcode, each specifying a different form of the operation. Some opcodes name instruction groups. For example, opcode Ox80 names a group of operations that have an immediate operand, and a register or memory operand. The group opcodes use an opcode extension field of 3 bits in the following byte, called the MOD RIM byte, to resolve the operation type. Opcodes for the entire <strong>TI486</strong>SLC/DLC instruction set are listed in the Instruction Set Summary Table. The opcodes are given in hex values unless shown within brackets ([ ]). Values shown in brackets are binary values. 7.2.3 vv Field The 1-bit field indicates the operand size during 16- and 32-bit data operations. Table 7-3. w Field Encoding wFIELD 0 1 OPERAND SIZE OPERAND SIZE 16-BIT DATA OPERATIONS 32-BIT DATA OPERATIONS 8 bits 8 bits 16 bits 32 bits 7.2.4 d Field The d field determines which operand is taken as the source operand and which operand is taken as the destination. Table 7-4. d Field Encoding d FIELD DIRECTION OF OPERATION SOURCE OPERAND DESIGNATION OPERAND 0 Register ---7 Register/Memory reg mod rim or mod ss-index-base 1 Register/Memory ---7 Register mod rim or mod ss-index-base reg 7-6 Instruction Set
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-21. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
Page 186 and 187: Functional Timing The TI486DLC/E sa
Page 188 and 189: Functional Timing 4.2.9 Hold Acknow
Page 190 and 191: Functional Timing Figure 4-23. Requ
Page 192 and 193: Functional Timing 4.2.10 Coprocesso
Page 194 and 195: Functional Timing 4.2.12 Power Mana
Page 196 and 197: Functional Timing Stopping the Inpu
Page 198 and 199: Electrical Specifications 5-1
Page 200 and 201: Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
Page 210 and 211: AC Characteristics Table 5-9. AC Ch
Page 212 and 213: AC Characteristics Table 5-11. AC C
Page 214 and 215: ____ AC Characteristics 5.5.3 RESET
Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 226 and 227: Pin Assignments Figure 6-3. TI486DL
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
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Page 250 and 251: Table 7-17. Instructions, Opcodes,
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Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
Page 276 and 277: Instruction Summary A.4.3 Resume No
Page 278 and 279: Instruction Summary A.4.6 Save LDTR
Page 280 and 281: 8MI Handler Example A.5 SMI Handler
Page 282 and 283: 8MI Handler Example execute_halt: C
Page 284 and 285: 8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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