TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
3.2.9 Coprocessor Interface
The coprocessor interface consists of the data bus, address bus, bus cycle
definition signals, and the coprocessor interface signals (BUSY, ERROR and
PEREQ). The TI486SLC/E automatically accesses dedicated coprocessor I/O
addresses 80 00F8h, 80 OOFCh, and 80 OOFEh to transfer opcodes and
operands to/from the coprocessor whenever a coprocessor instruction is
decoded. Coprocessor cycles can be either read or write and can be either
non-pipelined or pipelined. Coprocessor cycles must be terminated by
READY and, as with any other bus cycle, can be terminated as early as the
second bus state of the cycle.
BUSY, ERROR and PEREQ are asynchronous level-sensitive inputs used to
synchronize CPU and coprocessor operation. All three signals are sampled
at the beginning of phase 1 and must meet specified setup and hold times to
be recognized at a given CLK2 edge.
3.2.10 SMM Interface
3.2.10.1 SMI Handshake
System Management Mode (SMM) uses two TI486SLC/E pins, SMI and
SMADS. the bidirectional SMI pin is a non-maskable interrupt that is higher
priority than the NMI input. SMI must be active for at least four CLK2 periods
to be recognized by the TI486SLC/E. Once the TI486SLC/E recognizes the
active SMI input, the CPU drives the SMI pin low for the duration of the SMI
service routine.
The SMADS pin outputs the SMM Address Strobe that indicates a SMM
memory bus cycle is in progress and a valid SMM address is on the address
bus. The SMADS functional timing, output delay times and float delay times
are identical to the main memory address strobe (ADS) timing.
The functional timing for SMI interrupt is shown in Figure 3-22. Five significant
events take place during a TI486SLC/E SMI handshake:
1) The SMI input pin is driven active (low) by the system logic.
2) The CPU samples SM I active on the rising edge of CLK2 phase 1 .
3) Four CLK2s after sampling the SMI active, the CPU switches the SMI pin
to an output and drives SMllow.
4) Following execution of the RSM instruction, the CPU drives the SMI pin
high for two CLK2s indicating completion of the SMI service routine.
5) The CPU stops driving the SMI pin high and switches the SMI pin to an
input in preparation for the next SMI interrupt. The system logic is
responsible for maintaining the SMI pin at an inactive (high) level after the
pin has been changed to an input.
3-42
Tl486SLCIE Bus Interface