TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
3.2.3 Locked Bus Cycles
When the LOCK signal is asserted the TI486SLC/E microprocessor does not
allow other bus master devices to gain control of the system bus. LOCK is
driven active in response to executing certain instructions with the LOCK
prefix. The LOCK prefix allows indivisible read/modify/write operations on
memory operands. LOCK is also active during interrupt acknowledge cycles.
LOCK is activated on the CLK2 edge that begins the first locked bus cycle and
is deactivated when READY is returned at the end of the last locked bus cycle.
When using non-pipelined addressing, LOCK is asserted during phase 1 of
T1. When using pipelined addressing, LOCK is driven valid during phase 1 of
T1P.
Figure 3-4 through Figure 3-6 illustrate LOCK timing during non-pipelined
cycles and Figure 3-8 through Figure 3-11 cover the pipelined address case.
3.2.4 Interrupt Acknowledge (INTA) Cycles
The TI486SLC/E microprocessor is interrupted by an external source via an
input request on the INTR input (when interrupts are enabled). The
TI486SLC/E microprocessor responds with two locked interrupt acknowledge
cycles. These bus cycles are similar to read cycles. Each cycle is terminated
by READY sampled active as shown in Figure 3-13.
3-30
TI486SLCIE Bus Interface