TI486 Microprocessor - Al Kossow's Bitsavers

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Pin Assignments Figure 6-3. TI486DLCIE and TI486DLCIE- V Package Pins (Top View) p N M L K J H G F Pin # 1 Index Mark (On Top Side) E o c B GGGGGGG8GGG8G~) 1 8GGGGGG8GG88GG2 888GG8G88G8888 3 888 888 4 888 888 5 888 888 6 888 TI486DLC/E G 88 7 888 888 (TOP VIEW) 8 888 8SGg 888 SG8 10 888 8GG 11 888888GG8G88§B 12 88888888§S08BG 13 GG888GGGGG88GG 14 NC - No internal connection 6-7
Pin Assignments Table 6-3. TI486DLCIEand TI486DLCIE-V Signal Names Sorted by Pin Number PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME A1 Vee B9 BUSY 03 A9 H1 A17 L13 08 N7 Vee A2 Vss B10 W/R 012 Vce H2 A18 L14 06 N8 023 A3 A3 B11 Vss 013 NA H3 A19 M1 A26 N9 021 A4 SUSP B12 KEN 014 HOLO H12 00 M2 A29 N10 017 A5 Vce B13 BE2 E1 A14 H13 01 M3 Vcc N11 016 A6 Vss B14 Vss E2 A13 H14 02 M4 Vss N12 012 A7 Vee e1 A8 E3 A12 J1 A20 M5 031 N13 011 A8 ERROR C2 A7 E12 BEO J2 Vss M6 028 N14 09 A9 Vss C3 A6 E13 FLUSH J3 Vss M7 Vcc P1 A30 A10 Vee e4 A2 E14 AOS J12 Vss M8 Vss P2 Vec A11 O/G C5 Vce F1 A15 J13 Vss M9 020 P3 030 A12 MIlO C6 SMAOS F2 Vss J14 03 M10 Vss P4 029 A13 BE3 e7 SMi F3 Vss K1 A21 M11 015 P5 026 A14 Vce C8 PEREQ F12 eLK2 K2 A22 M12 010 P6 Vss B1 Vss C9 RESET F13 A20M K3 A25 M13 Vcc P7 024 B2 A5 C10 LOCK F14 Vss K12 07 M14 HLOA P8 Vcc B3 A4 C11 Vss G1 A16 K13 05 N1 A27 P9 022 B4 SUSPA e12 Vcc G2 Vcc K14 04 N2 A31 P10 019 B5 Vss C13 BE1 G3 Vec L1 A23 N3 Vss P11 018 B6 NC C14 BS16 G12 Vcc L2 A24 N4 Vce P12 014 B7 INTR 01 A11 G13 REAOY L3 A28 N5 027 P13 013 B8 NMI 02 A10 G14 Vec L12 Vec N6 025 P14 Vss Table 6-4. TI486DLCIE and TI486DLCIE-V Pin Numbers Sorted by Signal Name SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME NO. A2 C4 A23 L1 04 K14 026 P5 susP A4 Vss A2 A3 A3 A24 L2 05 K13 027 N5 SUSPA B4 Vss A6 A4 B3 A25 K3 06 L14 028 M6 Vcc A1 Vss A9 A5 B2 A26 M1 07 K12 029 P4 Vcc A5 Vss B1 A6 C3 A27 N1 08 L13 030 P3 Vee A7 Vss B5 A7 C2 A28 L3 09 N14 031 M5 Vcc A10 Vss B11 A8 C1 A29 M2 010 M12 ERROR A8 Vcc A14 Vss B14 A9 03 A30 P1 011 N13 FLUSH E13 Vee e5 Vss e11 A10 02 A31 N2 012 N12 HLOA M14 Vcc C12 Vss F2 A11 01 AOS E14 013 P13 HOLO 014 Vcc 012 Vss F3 A12 E3 BEO E12 014 P12 INTR B7 Vee G2 Vss F14 A13 E2 BE1 C13 015 M11 KEN B12 Vcc G3 Vss J2 A14 E1 BE2 B13 016 N11 LOCK C10 Vcc G12 Vss J3 A15 F1 BE3 A13 017 N10 MIlO A12 Vce G14 Vss J12 A16 G1 BS16 C14 018 P11 NA 013 Vcc L12 Vss J13 A17 H1 BUSY B9 019 P10 NC B6 Vce M3 Vss M4 A18 H2 CLK2 F12 020 M9 NMI B8 Vce M7 Vss M8 A19 H3 O/G A11 021 N9 PEREO C8 Vcc M13 Vss M10 A20 J1 00 H12 022 P9 REAOY G13 Vcc N4 Vss N3 A20M F13 01 H13 023 N8 RESET C9 Vce N7 Vss P6 A21 K1 02 H14 024 P7 SMI C7 Vcc P2 Vss P14 A22 K2 03 J14 025 N6 SMAOS C6 Vcc P8 W/R B10 6-8 Mechanical Specifications
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
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Interrupts and Exceptions Table 2-2
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System Management Mode 2.6 System M
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System Management Mode Figure 2-29.
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System Management Mode The new SMM
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System Management Mode During SMM o
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Protection The Current Privilege Le
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Virtual 8086 Mode 2.9 Virtual 8086
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TI486SLC/E Bus Interface 3-1
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Chapter 3 TI486SLC/E Bus Interface
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Overview Table 3-1. TI486SLCIE Sign
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Overview Table 3-2. Terminal Functi
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Overview 3.1.1 Bus Cycle Definition
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Overview Table 3-5 shows the state
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Functional Timing Figure 3-3. Bus A
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Functional Timing 3.2.2.1 Bus Cycle
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Functional Timing Non-Pipelined Wai
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Functional Timing Because of the de
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Functional Timing Pipelined Wait St
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Functional Timing Initiating and Ma
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Functional Timing Figure 3-12. Comp
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Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-21. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
Page 176 and 177: Functional Timing Pipelined Cycles
Page 178 and 179: Functional Timing LOCK is activated
Page 180 and 181: Functional Timing 4.2.6 Halt and Sh
Page 182 and 183: Functional Timing Figure 4-17. Pipe
Page 184 and 185: Functional Timing Figure 4-19. Non-
Page 186 and 187: Functional Timing The TI486DLC/E sa
Page 188 and 189: Functional Timing 4.2.9 Hold Acknow
Page 190 and 191: Functional Timing Figure 4-23. Requ
Page 192 and 193: Functional Timing 4.2.10 Coprocesso
Page 194 and 195: Functional Timing 4.2.12 Power Mana
Page 196 and 197: Functional Timing Stopping the Inpu
Page 198 and 199: Electrical Specifications 5-1
Page 200 and 201: Chapter 5 Electrical Specifications
Page 202 and 203: ElectricalConnecnons It is recommen
Page 204 and 205: Recommended Operating Conditions 5.
Page 206 and 207: DC Electrical Characteristics Table
Page 208 and 209: AC Characteristics Figure 5-2. TI48
Page 210 and 211: AC Characteristics Table 5-9. AC Ch
Page 212 and 213: AC Characteristics Table 5-11. AC C
Page 214 and 215: ____ AC Characteristics 5.5.3 RESET
Page 220 and 221: Mechanical Specifications 6-1
Page 222 and 223: Chapter 6 Mechanical Specifications
Page 224 and 225: Pin Assignments Table 6-1. TI486SLC
Page 228 and 229: Package Dimensions 6.2 Package Dime
Page 230 and 231: Thermal Characteristics 6.3 Thermal
Page 232 and 233: Instruction Set 7-1
Page 234 and 235: Chapter 7 Instruction Set This sect
Page 236 and 237: Instruction Fields 7.2 Instruction
Page 238 and 239: Instruction Fields 7.2.5 reg Field
Page 240 and 241: Instruction Fields Table 7-7. mod r
Page 242 and 243: Instruction Fields 7.2.11 sreg3 Fie
Page 244 and 245: Clock Count Summary 7.4 Clock Count
Page 246 and 247: --- --;.J -L 01 Table 7-17. Instruc
Page 248 and 249: I . ~ -.....J Table 7-17. Instructi
Page 250 and 251: Table 7-17. Instructions, Opcodes,
Page 254 and 255: -....J N (J.) Table 7-17. Instructi
Page 256 and 257: I I i I i Table 7-17. Instructions,
Page 258 and 259: ...... ...... '" Table 7-17. Instru
Page 260 and 261: -....J N co Table 7-17. Instruction
Page 262 and 263: "-.I ~ Table 7-17. Instructions, Op
Page 266 and 267: U Appendix A TI486 SMM Pro rammer's
Page 268 and 269: SMM Implementation A.2 SMM Implemen
Page 270 and 271: Figure A-1. SMM Memory Space Header
Page 272 and 273: SMM Implementation 6) NMI is the on
Page 274 and 275: Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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i**********************************
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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