TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Once a bus cycle is in progress and the current address has been valid for one
entire bus state, the NA input is sampled at the end of every phase one until
the bus cycle is acknowledged. Once NA is sampled active, the TI486DLC/E
microprocessor is free to drive a new address and bus cycle definition on the
bus as early as the next bus state and as late as the last bus state in the cycle.
Figure 4-10 illustrates the fastest transition possible to pipelined addressing
following an idle bus state. In Cycle 1, NA is driven during state T2. Thus, Cycle
1 makes the transition to pipelined address timing, since it begins with T1 but
ends with T2P. Because the address for Cycle 2 is available before Cycle 2
begins, Cycle 2 is called a pipelined bus cycle, and it begins with a T1 P state.
Cycle 2 begins as soon as READY asserted terminates Cycle 1.
Figure 4-10. Fastest Transition to Pipelined Address Following Idle Bus State
Idle 1
1
.~
1
1 T1
Cycle 1
Non-Pipelined
(Write)
Cycle 2
Pipelined 1
(Read) 1
--1 l1li --I~
T1P 1 T2P :
Cycle 3
Pipelined 1
(Write) 1
·I~
1 1
1 T2P 1 T1P
Cycle 4
Pipelined
(Read)
1 Idle
1
.II1II
CLK2
A31-A2 _
BE3-BEO,
MIlO, Die
Note:
LOCK " : Valid 1, «
« Vflid 2
« V+ 3
: Valid t ~
1 1 1 1 1 1 1 1 1 1 1 1
031-00 -L--.L-{,..---O-ut-1---}-....l-~ < Out 3 )-....l--....l-~-_
I I i I ~ i I I I ~
Following any idle bus state (Ti) the address is always non-pipe lined and NA is sampled only during wait states. To start
address pipelining after an idle state requires a non-pipelined cycle with at least one wait state (Cycle 1 above). The
pipelined cycles (2,3, and 4 above) are shown with various numbers of wait states.
Figure 4-11 illustrates transitioning to pipelined addressing during a burst of
bus cycles. Cycle 2 makes the transition to pipelined addressing. Comparing
Cycle 2 to Cycle 1 of Figure 3-10 illustrates that a transition cycle is the same
whenever it occurs consisting of at least T1, T2 (NA is asserted at that time),
and T2P (provided the TI486DLC/E microprocessor has an internal bus
request already pending). T2P states are repeated if wait states are added to
the cycle. Cycles 2, 3, and 4 in Figure 4-11 show that once address pipelining
is achieved it can be maintained with two-state bus cycles consisting only of
T1P and T2P.
4-28
Tl486DLCIE Bus Interface