TI486 Microprocessor - Al Kossow's Bitsavers

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Functional Timing As shown in Figure 3-18, the TI486SLC/E samples the A20M input on the rising edge of CLK2 corresponding to the beginning of phase 2 of the internal processor clock. If A20M is asserted and paging is not enabled, the TI486SLC/E masks the A20 signal internally starting with the next cache access and externally starting with the next bus cycle. If paging is enabled, the A20 signal is not masked regardless of the state of A20M. A20 remains masked until the access following detection of an inactive state on the A20M pin. A20M must be asserted for a minimum of two CLK2 periods and must meet specified setup and hold times to be recognized on a specific CLK2 edge. An alternative to using the A20M pin is provided by the NCO bit in the CCRO configuration register. The TI486SLC/E automatically does not cache accesses, to the first 64 KBytes and to 1 MByte + 64 KBytes, if the NCO bit is set. This prevents data within the wraparound memory area from residing in the internal cache and thus eliminates the need for masking A20 to the internal cache. Figure 3-18. Masking A20 Using A20M During Burst of Bus Cycles CLK2 A19-A1, 1 + 1 Cycle 1 1 Cycle 2 1 Cycle 3 1 Cycle 4 1 Idle 1 Non-Pipelined 1 Non-Pipelined 1 Pipelined 1 Pipelined 1 Idle (Write) .:. (Read) .~ (Write) .:. (Write) .1. 1 Ti 1 T1 1 T2 1 T1 1 T2 1 T2P 1 T1 P 1 T2P 1 T1 P 1 T21 1 Ti « 1 B~t:C~ ~ vai lid 1 \ti alid 2 M/IO,D/C~ W/R !riri,"""'-r-l,--_... '__-' « I Valid 2; « « Vjlid 3 015-00 ~---~-< : Out 1 I I : >-t--i-- ~: Out 3 : 3-37
Functional Timing 3.2.8 Hold Acknowledge State The hold acknowledge state provides the mechanism for an external device in a TI486SLC/E system to acquire the TI486SLC/E system bus while the TI486SLC/E is held in an inactive bus state. This allows external bus masters to take control of the TI486SLC/E bus and directly access system hardware in a shared manner with the TI486SLC/E. The TI486SLC/E continues to execute instructions out of the cache (if enabled) until a system bus cycle is required. The hold acknowledge state (Th) is entered in response to assertion of the HOLD input. in the hold acknowledge state, the TI486SLC/E microprocessor floats all output and bidirectional signals, except for HLDA and SUSPA. HLDA is asserted as long as the TI486SLC/E CPU remains in the hold acknowledge state and all inputs except HOLD, FLUSH, FLT, SUSP and RESET are ignored. State Th may be entered directly from a bus idle state, as in Figure 3-19, or after the completion of the current physical bus cycle if the LOCK signal is not asserted, as in Figure 3-20 and Figure 3-21. The CPU samples the HOLD input on the rising edge of CLK2 corresponding to the beginning of phase 1 of internal processor clock. HOLD must meet specified setup and hold times to be recognized at a given CLK2 edge. The hold acknowledge state is exited in response to the HOLD input being negated. The next bus start is an idle state (Ti) if no bus request is pending, as in Figure 3-19. If a bus request is internally pending, as in Figure 3-20 and Figure 3-21, the next bus state is T1. State Th is also exited in response to RESET being asserted. If HOLD remains asserted when RESET goes inactive, the TI486SLC/E enters the hold acknowledge state before performing any bus cycles provided HOLD is still asserted when the CPU is ready to perform its first bus cycle. If a rising edge occurs on the edge-triggered NMI input while in state Th, the event is remembered as a non-maskable interrupt 2 and is serviced when the state is exited. 3-38 TI486SLCIE Bus Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
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Tl486DLCIE Overview 1.4 TI486DLC/E
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TI486DLCIE Overview The TI486DLC/E
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Power Management / System Managemen
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Programming Interface 2-1
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Chapter 2 In this chapter, the inte
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Processor Initialization Table 2-1.
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Instruction Set Overview 2.2 Instru
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Register Set 2.3 Register Set There
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Register Set Pointer and Index Regi
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Register Set 2.3.1.2 Segment Regist
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Register Set 2.3.1.3 Instruction Po
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Register Set 2.3.2 System Register
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Register Set 2.3.2.1 Control Regist
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Register Set 2.3.2.2 Descriptor Tab
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Register Set Table 2-6. Segment Des
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Register Set During task switching,
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Register Set The CCRO register (Tab
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Register Set Table 2-9. TI486DLCIE
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Register Set Table 2-12. ARR 1-ARR4
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Register Set 2.3.2.6 Test Registers
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Register Set Table 2-14. TR6 and TR
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Address Spaces 2.4 Address Spaces T
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Address Spaces 2.4.2 Memory Address
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Address Spaces Figure 2-21. Real Mo
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Address Spaces Figure 2-24. Paging
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Interrupts and Exceptions 2.5 Inter
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Interrupts and Exceptions 2.5.3 Int
Page 82 and 83: Interrupts and Exceptions Table 2-2
Page 84 and 85: System Management Mode 2.6 System M
Page 86 and 87: System Management Mode Figure 2-29.
Page 88 and 89: System Management Mode The new SMM
Page 90 and 91: System Management Mode During SMM o
Page 92 and 93: Protection The Current Privilege Le
Page 94 and 95: Virtual 8086 Mode 2.9 Virtual 8086
Page 96 and 97: TI486SLC/E Bus Interface 3-1
Page 98 and 99: Chapter 3 TI486SLC/E Bus Interface
Page 100 and 101: Overview Table 3-1. TI486SLCIE Sign
Page 102 and 103: Overview Table 3-2. Terminal Functi
Page 108 and 109: Overview 3.1.1 Bus Cycle Definition
Page 110 and 111: Overview Table 3-5 shows the state
Page 112 and 113: Functional Timing Figure 3-3. Bus A
Page 114 and 115: Functional Timing 3.2.2.1 Bus Cycle
Page 116 and 117: Functional Timing Non-Pipelined Wai
Page 118 and 119: Functional Timing Because of the de
Page 120 and 121: Functional Timing Pipelined Wait St
Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
Page 128 and 129: Functional Timing Shutdown Indicati
Page 130 and 131: Functional Timing Figure 3-17. Pipe
Page 134 and 135: Functional Timing Figure 3-19. Requ
Page 136 and 137: Functional Timing Figure 3-21. Requ
Page 138 and 139: Functional Timing Figure 3-22. 8MI
Page 140 and 141: Functional Timing HALT Initiated Su
Page 142 and 143: Functional Timing 3.2.12 Float Figu
Page 144 and 145: TI486DLC/E Bus Interface 4-1
Page 146 and 147: Chapter 4 TI486DLC/E Bus Interface
Page 148 and 149: Overview Table 4-1. TI486DLCIE SIgn
Page 156 and 157: Overview Table 4-6. Signal States D
Page 158 and 159: Overview 4.1.2 Power Management 4.1
Page 160 and 161: Functional Timing 4.2 Functional Ti
Page 162 and 163: Functional Timing The TI486DLC/E da
Page 164 and 165: Functional Timing Non-Pipelined Rea
Page 166 and 167: Functional Timing Initiating and Ma
Page 168 and 169: Functional Timing Figure 4-8. Faste
Page 170 and 171: Functional Timing Figure 4-9. Vario
Page 172 and 173: Functional Timing Once a pipelined
Page 174 and 175: Functional Timing 4.2.3 Bus Cycles
Page 176 and 177: Functional Timing Pipelined Cycles
Page 178 and 179: Functional Timing LOCK is activated
Page 180 and 181: Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing Figure 4-23. Requ
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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