TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Figure 4-14. Pipelining and as 16
previous:
Cycle
A Transfer Requiring Two Cycles
on 16-Bit Bus
(__-------------)l,------------__
"
Cycle 1A 1 Cycle 1B
Pipelined 1 Non-Pipelined
Write, Part One
Write, Part Two
~
.1.
1 1
1 T2P 1 T1P 1 T2 T2 1 T1 T2 1
1
1
~ ..
T2 1
Cycle 2 1
Non-Pipelined 1 Idle
Read
.1
1
T1 T2 1 T2P 1 Ti
CLK2
Always Inactive
During Part 2 1
B~~~B~i ~ V~lid 1 II I :x V~lid 2 Valid 3
MilO, DIC -," iii
W/R J/ : : :\: :
1 1 1 1 1 1 1 1
AD8~~~--~--~~~--~~~ :\~~: __ ~
1 1 NA must be negated in these T's to allow
I 1 recognilion of as~erted B81,6 in final T2S.
B816~~~~~~~~~~~~~~~~~~~~~~~~_;I--~~~~8
1 1 1 16-Bit 1 1 1 16-Bit 1 1 1 1
~ 1 I Bus Size 1 1 1 Bus Size 1 1 1 1 1
REAOY~ ~~~~,......: ~'I~I 'I~i 'I ~
LOCK "0 :: dJ5-dO vr: lid 1 :: d31~16 I:X ; Valid r d1~
015-00 -1--G--<
~ut . X O~t >-+----t--$--1
031-016 -~-tf>--~
1 I I I 1 1 1
On = physical data pin n.
dn = logical data bit n.
Cycle 1 A is pipelined. Cycle 1 B cannot be pipelined, but its address can be inferred from cycle 1 to externally simulate
address pipelining during cycle 1 B.
4.2.4 Locked Bus Cycles
When the LOCK signal is asserted, the TI486DLC/E microprocessor does not
allow other bus master devices to gain control of the system bus. LOCK is
driven active in response to executing certain instructions with the LOCK
prefix. The LOCK prefix allows indivisible read/modify/write operations on
memory operands. LOCK is also active during interrupt acknowledge cycles.
4-34
Tl486DLCIE Bus Interface