TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Figure 3-11 illustrates transitioning to pipelined addressing during a burst of
bus cycles. Cycle 2 makes the transition to pipelined addressing. Comparing
Cycle 2 to Cycle 1 of Figure 3-10 illustrates that a transition cycle is the same
whenever it occurs consisting of at least T1, T2 (NA is asserted at that time),
and T2P (provided the TI486SLC/E microprocessor has an internal bus
request already pending). T2P states are repeated if wait states are added to
the cycle. Cycles 2, 3, and 4 in Figure 3-11 show that once address pipe lining
is achieved it can be maintained with two-state bus cycles consisting only of
T1P and T2P.
Once a pipelined bus cycle is in progress, pipelined timing is maintained for
the next cycle by asserting NA and detecting that the TI486SLC/E
microprocessor enters T2P during the current bus cycle. The current bus cycle
must end in state T2P for pipelining to be maintained in the next cycle. T2P is
identified by the assertion of ADS. Figure 3-10 and Figure 3-11 each show
pipelining ending after Cycle 4. This occurred because the TI486SLC/E CPU
did not have an internal bus request prior to the acknowledgment of Cycle 4.
Figure 3~ 11. Transitioning to Pipelined Address During Burst of Bus Cycles
CLK2
Idle
I Cycle 1
1 Non-Pipelined
+
(Write)
Ti 1
A23-A1,~1 I
BHE, BLs
M/IO,D/C
T1
I
1
.1 ..
1
I
Cycle 2
Non-Pipelined
(Read)
I
I
.~
T1 T2P I
wlR i~~&"--r-l------I-'
Cycle 3 1
Pipelined I
(Write) .1 ..
1 1
T1P I T2P I T1P
Cycle 4
Pipelined
(Read)
Note:
, 1.1
•
I
«
I
:
1
Valid
I
1 1 1
~i ~
V~lid3 ~
V~lid4 ~
«
2;
Out 1 }-T--I- 1 1-$: In 2 < Out 3 I }-I- 1 In4--1
:
- 1
1 I I I 1
I I I I I I I I
Following any idle bus state (Ti), addresses are non-pipelined bus cycles, NA is sampled only during wait states.
Therefore, to begin address pipelining during a group of non-pipelined bus cycles requires a non-pipelined cycle with at
least one wait state (Cycle 2 above).
The complete bus state transition diagram, including operation with pipelined
address is given in Figure 3-12. This is a superset of the diagram for
non-pipelined address. The three additional bus states for pipelined address
are shaded.
3-28
TI486SLCIE Bus Interface