TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
3.2.2.1 Bus Cycles Using Non-Pipelined Addressing
Non-Pipelined Bus States
The shortest time unit of bus activity is a bus state, commonly called a T state.
A bus state is one internal processor clock period (two CLK2 periods) in
duration. A complete data transfer occurs during a bus cycle, composed oftwo
or more bus states.
The first state of a non-pipelined bus cycle is called T1. During phase one (first
CLK2) of T1 , the address bus and bus cycle definition signals are driven valid
and, to signal their availability, address strobe (ADS) is simultaneously
asserted.
The second bus state of a non-pipelined cycle is called T2. T2 terminates a bus
cycle with the assertion of the READY input and valid data is either input or
output depending on the bus cycle type. The fastest TI486SLC/E
microprocessor bus cycle requires only these two bus states. READY is
ignored at the end of the T1 state.
Three consecutive bus read cycles, each consisting of two bus states, are
shown in Figure 3-4.
Figure 3-4. Fastest Non-Pipelined Read Cycles
CLK2
r Non-Pipelined ----'r Non-Pipelined .14 Non-Pipelined ~
1 Cycle 1 1 Cycle 2 1 Cycle 3 1
1 (Read) 1 (Read) 1 (Read) 1
1 T1 1 T2 1 T1 1 T2 1 T1 T2 1
11 21 11 2 11 21 11 2 11 11 2 1
1 1 1 1 1 1 1
A23-~~6~~/~, ~M ---I~I-""""'--V""~I-id-1 ---Ico~-'---V--~-lid-2---:I-X""""'--v"":al-id-3--"'~~-
READY
015-00
(Input During Read)
1 1 1 1 1 1 1
l\ V,------il.~ V,------i\:\ II :'--
1 ~-~I 1 ~-~I 1 ~-~I 1
NA --~I--------I--------I--------I--------I------~I--------I----
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
X Valid 1 ~ ~alid 2 X Valid 3 «
i
i
1 1 1 1 1 1 1
~--r--~--r--~--r--~
1 : 1 : 1 : 1
Note: Fastest non-pipelined bus cycles consist of T1 and T2.
3-19