TI486 Microprocessor - Al Kossow's Bitsavers

Overview
Table 4-1. TI486DLCIE SIgnal Summary
SIGNAL SIGNAL NAME SIGNAL GROUP
A20M
Address Bit 20 Mask
A31-A2 Address Bus Lines Address bus
ADS Address Strobe Bus cycle control
BE3-BEO Byte enables Address bus
BS16 Bus size 16 Bus cycle control
BUSY Processor extension busy Coprocessor interface
CLK2
D31-DO
2X clock input
Data bus
DIC Data/control Bus cycle definition
ERROR Processor extension error Coprocessor interface
FLUSH Cache flush Internal cache interface
HLDA Hold acknowledge Bus arbitration
HOLD Hold request Bus arbitration
INTR Maskable interrupt request Interrupt control
KEN Cache enable Internal Cache interface
LOCK Bus lock Bus cycle definition
MilO Memory/input-output Bus cycle definition
NA Next address request Bus cycle control
NMI Non-maskable interrupt request Interrupt control
PEREQ Processor extension request Coprocessor interface
READY Bus ready Bus cycle control
RESET
Reset
SMADS SMM address strobe Bus cycle control
SMI System management interrupt Interrupt control
SUSP Suspend request Power management
SUSPA Suspend acknowledge Power management
WIR Writelread Bus cycle definition
The following sections describe the signals and their functional timing
characteristics. Additional signal information may be found in Chapter 5,
Electrical Specifications. Chapter 5 documents the dc and ac characteristics
for the signals including voltage levels, propagation delays, setup times, and
hold times. Specified setup and hold times must be met for proper operation
of the TI486DLC/E.
4-5