TI486 Microprocessor - Al Kossow's Bitsavers

Functional Timing
Figure 3-12. Complete Bus States
HOLD Asserted
HOLD Asserted
HOLD Negated·
Request Pending
READY Asserted·
HOLD Asserted
~---r-- READY Asserted·
HOLD Negated·
No Request
READY Asserted·
HOLD Asserted
(No Request +
HOLD Asserted) .
NA Asserted·
READY Negated
I
NA Asserted·
(HOLD Asserted +
No Request)
I
I
I
I
I
I
I
I
I NA Negated I
Request Pending·
HOLD Negated
READY Asserted·
HOLD Negated·
No Request
READY Asserted·
HOLD Negated·
Request Pending
READY Negated·
(No Request + /
HOLD Asserted)
READY Negated·
NA Asserted·
HOLD Negated
Request Pending
READY Negated
Request Pending
HOLD Asserted
NA Asserted·
HOLD Negated·
Request Pending
READY Asserted
READY Negated
Bus States:
T1 - First clock of a non-pipelined bus cycle (QEU drives new address and asserts ADS).
T2 - Subsequent clocks of a bus cycle when NA has not been sampled asserted in the current bus cycle.
T21 - Subsequent clocks of a bus cycle when NA has been sampled asserted in the current bus cycle but there
is not yet an internal bus request pendio.9.JCPU drives new address and asserts ADS).
T2P - Subsequent clocks of a bus cycle when NA has been sampled asserted in the current bus cycle and there
is an internal bus request pending (CPU drives new address and asserts ADS).
T1 P - First clock of a pipelined bus cycle.
Ti - Idle state.
Th - Hold Acknowledge state (CPU asserts HLDA).
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