TI486 Microprocessor - Al Kossow's Bitsavers

Overview
Table 4-2. Terminal Functions (Continued)
NAME
PIN
NO.
1/0
DESCRIPTION
HOLD D14 I Hold Request (active high). This input is used to indicate that another bus master
requests control of the local bus. The bus arbitration (HOLD, HLDA) signals allow the
TI486DLC/E to relinquish control of its local bus when requested by another bus master
device. Once the processor has relinquished its bus (3-stated), the bus master device
can then drive the local bus signals.
After recognizing the HOLD request and completing the current bus cycle or sequence
of locked bus cycles, the TI486DLC/E responds by floating the local bus and asserting
the hold acknowledge (HLDA) output.
Once HLDA is asserted, the bus remains granted to the requesting bus master until
HOLD becomes inactive. When the TI486DLC/E recognizes HOLD is inactive, it
simultaneously drives the local bus and drives HLDA inactive. External pullup resistors
may be required on some of the TI486DLC/E 3-state outputs to guarantee that they
remain inactive while in a hold acknowledge state.
The HOLD input is not recognized while RESET is active. If HOLD is asserted while
RESET is active, RESET has priority and the TI486DLC/E places the bus into an idle
state instead of a hold acknowledge state. The HOLD input is also recognized during
suspend mode provided that the CLK2 input has not been stopped. HOLD is
level-sensitive and must meet specified setup and hold times for correct operation.
INTR B7 I Maskable Interrupt Request. This is a level-sensitive input that causes the processor
to suspend execution ofthe current instruction stream and begin execution of an interrupt
service routine. The INTR input can be masked (ignored) through the Flags Register IF
bit. When unmasked, the TI486DLC/E responds to the INTR input by issuing two locked
interrupt acknowledge cycles. To assure recognition of the INTR request, INTR must
remain active until the start of the first interrupt acknowledge cycle.
KEN B12 I Cache Enable (active low). This is an input which indicates that the data being returned
during the current cycle is cacheable. When KEN is active and the TI486DLC/E is
performing a cacheable code fetch or memory data read cycle, the cycle is transformed
into a cache fill. Use of the KEN input to control cacheability is optional. The
non-cacheable region registers can also be used to control cacheablity. Memory
addresses specified by the non-cacheable region registers are not cacheable regardless
of the state of KEN. I/O accesses, locked reads, SMM address space accesses, and
interrupt acknowledge cycles are never cached.
During cached code fetches, two contiguous read cycles are performed to completely
fill the 4-byte cache line. KEN must be asserted during both read cycles in order to cause
a cache line fill. During cached data reads, the TI486DLC/E performs only those bus
cycles necessary to supply the required data to complete the current operation. Valid bits
are maintained for each byte in the cache line, thus allowing data operands of less than
4 bytes to reside in the cache.
During any cache fill cycle with KEN asserted, the TI486DLC/E ignores the state of the
byte enables (BE3 - BEO) and always writes two bytes of data into the cache. The KEN
input is ignored following reset and can be enabled using the KEN bit in the CCRO
configuration register.
KEN is internally connected to a pullup resistor to prevent it from floating active when left
unconnected.
LOCK C10 I LOCK (active low). LOCK is asserted to deny control of the CPU bus to other bus
masters. The LOCK signal may be explicitly activated during bus operations by including
the LOCK prefix on certain instructions. LOCK is always asserted during descriptor and
page table updates, interrupt acknowledge sequences and when executing the XCHG
instruction. The TI486DLC/E does not enter the hold acknowledge state in response to
HOLD while the LOCK input is active.
MilO A12 01Z Memory/lO. This signal is low during I/O read and write cycles and is high during
memory cycles.
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