TI486 Microprocessor - Al Kossow's Bitsavers

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Interrupts and Exceptions 2.5 Interrupts and Exceptions The processing of either an interrupt or an exception changes the normal sequential flow of a program by transferring program control to a selected service routine. Except for SMM interrupts, the location of the selected service routine is determined by one of the interrupt vectors stored in the interrupt descriptor table. All true interrupts are hardware interrupts and are generated by signal sources external to the CPU. All exceptions, including so-called software interrupts, are produced internally by the CPU. 2.5.1 Interrupts External events can interrupt normal program execution by using one of the three interrupt pins on the T1486. • Non-maskable Interrupt (NMI pin) • Maskable Interrupt (INTR pin) • 8MM Interrupt (8MI pin) For most interrupts, program transfer to the interrupt routine occurs after the current instruction has been completed. When the execution returns to the original program, it begins immediately following the interrupted instruction. The NMI interrupt cannot be masked by software and always uses interrupt vector 2 to locate its service routine. Since the interrupt vector is fixed and is supplied internally, no interrupt acknowledge bus cycles are performed. This interrupt is usually reserved for unusual situations such as parity errors and has priority over INTR interrupts. Once NMI processing has started, no additional NMls are processed until an IRET instruction is executed, typically at the end of the NMI service routine. If NMI is re-asserted priortothe execution ofthe IRETinstruction, one and only one NMI rising edge is stored and then processed after execution of the next IRET. During the NMI service routine, maskable interrupts are still enabled. If an unmasked INTR occurs during the NMI service routine, the INTR is serviced and execution returns to the NMI service routine following the next IRET. If a HALT instruction is executed within the NMI service routine, the TI486 restarts execution only in response to RESET, an unmasked INTR, or an 8MM interrupt. NMI does not restart CPU execution under this condition. The INTR interrupt is unmasked when the Interrupt Enable Flag (IF) in the EFLAGS register is set to 1. With the exception of string operations, INTR interrupts are acknowledged between instructions. Long string operations have interrupt windows between memory moves that allow INTR interrupts to be acknowledged. 2-45
Interrupts and Exceptions When an INTR interrupt occurs, the CPU performs two locked interrupt acknowledge bus cycles. During the second cycle, the CPU reads an 8-bit vector which is supplied by an external interrupt controller. This vector selects which of the 256 possible interrupt handlers will be executed in response to the interrupt. The SMM interrupt has higher priority than either the INTR or NMI. After SMI is asserted, program execution is passed to an SMI service routine which runs in SMM address space reserved for this purpose. The remainder of this section does not apply to the SMM interrupts. SMM interrupts are described in greater detail later in this chapter. 2.5.2 Exceptions Exceptions are generated by an interrupt instruction or a program error. Exceptions are classified as traps, faults, or aborts depending on the mechanism used to report them and the restartability of the instruction which first caused the exception. A trap exception is reported immediately following the instruction that generated the trap exception. Trap exceptions are generated by execution of a software interrupt instruction during single stepping, at a breakpoint, or by software interrupt instruction (lNT 0, INT 3, INT n, BOUND) by a single-step operation, or by a data breakpoint. Software interrupts can be used to simulate hardware interrupts. For example, an INT n instruction causes the processor to execute the interrupt service routine pointed to by the nth vector in the interrupt table. Execution of the interrupt service routine occurs regardless of the state of the IF flag in the EFLAGS register. The one-byte INT 3, or breakpoint-interrupt (vector 3), is a particular case of the INT n instruction. By inserting this one-byte instruction in a program, the user can set breakpoints in code that can be used during debug. Single-step operation is enabled by setting the TF bit in the EFLAGS register. When TF is set, the CPU generates a debug exception (vector 1) after the execution of every instruction. Data breakpoints also generate a debug exception and are specified by loading the debug registers (DRO-DR7) with the appropriate values. A fault exception is caused by a program error and is reported prior to completion of the instruction that generated the exception. By reporting the fault prior to instruction completion, the CPU is left in a state which allows the instruction to be restarted and the effects of the faulting instruction to be nullified. Fault exceptions include divide-by-zero errors, invalid opcodes, page faults, and coprocessor errors. Debug exceptions (vector 1) are also handled as faults (except for data breakpoints and Single-step operations). After execution of the fault service routine, the instruction pointer points to the instruction that caused the fault. An abort exception is a type of fault exception that is severe enough that the CPU cannot restart the program at the faulting instruction. Abort exceptions include the double fault (vector 8) and coprocessor segment overrun (vector 9). 2-46 Programming Interface
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.TEXAS INSTRUMENTS TI486 Microproce
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TI486 Microprocessor Reference Guid
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Preface Read This First About This
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About This Manual Appendix D Orderi
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Contents 1 Product Overview .......
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Contents 5.5 AC Characteristics . .
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1-1 TI486SLC/E Functional Block Dia
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Figures 4-27 SUSP Initiated Suspend
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Tables 5-3 Absolute Maximum Ratings
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Product Overview 1-1
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Chapter 1 Product Overview Features
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1.2 Differences Between the TI486SL
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Tl486SLCIE Overview Figure 1-2. TI4
Page 28 and 29: Tl486DLCIE Overview 1.4 TI486DLC/E
Page 30 and 31: TI486DLCIE Overview The TI486DLC/E
Page 32 and 33: Power Management / System Managemen
Page 34 and 35: Programming Interface 2-1
Page 36 and 37: Chapter 2 In this chapter, the inte
Page 38 and 39: Processor Initialization Table 2-1.
Page 40 and 41: Instruction Set Overview 2.2 Instru
Page 42 and 43: Register Set 2.3 Register Set There
Page 44 and 45: Register Set Pointer and Index Regi
Page 46 and 47: Register Set 2.3.1.2 Segment Regist
Page 48 and 49: Register Set 2.3.1.3 Instruction Po
Page 50 and 51: Register Set 2.3.2 System Register
Page 52 and 53: Register Set 2.3.2.1 Control Regist
Page 54 and 55: Register Set 2.3.2.2 Descriptor Tab
Page 56 and 57: Register Set Table 2-6. Segment Des
Page 58 and 59: Register Set During task switching,
Page 60 and 61: Register Set The CCRO register (Tab
Page 62 and 63: Register Set Table 2-9. TI486DLCIE
Page 64 and 65: Register Set Table 2-12. ARR 1-ARR4
Page 66 and 67: Register Set 2.3.2.6 Test Registers
Page 68 and 69: Register Set Table 2-14. TR6 and TR
Page 70 and 71: Address Spaces 2.4 Address Spaces T
Page 72 and 73: Address Spaces 2.4.2 Memory Address
Page 74 and 75: Address Spaces Figure 2-21. Real Mo
Page 76 and 77: Address Spaces Figure 2-24. Paging
Page 80 and 81: Interrupts and Exceptions 2.5.3 Int
Page 82 and 83: Interrupts and Exceptions Table 2-2
Page 84 and 85: System Management Mode 2.6 System M
Page 86 and 87: System Management Mode Figure 2-29.
Page 88 and 89: System Management Mode The new SMM
Page 90 and 91: System Management Mode During SMM o
Page 92 and 93: Protection The Current Privilege Le
Page 94 and 95: Virtual 8086 Mode 2.9 Virtual 8086
Page 96 and 97: TI486SLC/E Bus Interface 3-1
Page 98 and 99: Chapter 3 TI486SLC/E Bus Interface
Page 100 and 101: Overview Table 3-1. TI486SLCIE Sign
Page 102 and 103: Overview Table 3-2. Terminal Functi
Page 108 and 109: Overview 3.1.1 Bus Cycle Definition
Page 110 and 111: Overview Table 3-5 shows the state
Page 112 and 113: Functional Timing Figure 3-3. Bus A
Page 114 and 115: Functional Timing 3.2.2.1 Bus Cycle
Page 116 and 117: Functional Timing Non-Pipelined Wai
Page 118 and 119: Functional Timing Because of the de
Page 120 and 121: Functional Timing Pipelined Wait St
Page 122 and 123: Functional Timing Initiating and Ma
Page 124 and 125: Functional Timing Figure 3-12. Comp
Page 126 and 127: Functional Timing Figure 3-13. Inte
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Functional Timing Shutdown Indicati
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Functional Timing Figure 3-17. Pipe
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Functional Timing As shown in Figur
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Functional Timing Figure 3-19. Requ
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Functional Timing Figure 3-22. 8MI
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Functional Timing HALT Initiated Su
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Functional Timing 3.2.12 Float Figu
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TI486DLC/E Bus Interface 4-1
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Chapter 4 TI486DLC/E Bus Interface
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Overview Table 4-1. TI486DLCIE SIgn
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Overview Table 4-2. Terminal Functi
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Overview Table 4-6. Signal States D
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Overview 4.1.2 Power Management 4.1
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Functional Timing 4.2 Functional Ti
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Functional Timing The TI486DLC/E da
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Functional Timing Non-Pipelined Rea
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Functional Timing Initiating and Ma
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Functional Timing Figure 4-8. Faste
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Functional Timing Figure 4-9. Vario
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Functional Timing Once a pipelined
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Functional Timing 4.2.3 Bus Cycles
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Functional Timing Pipelined Cycles
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Functional Timing LOCK is activated
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Functional Timing 4.2.6 Halt and Sh
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Functional Timing Figure 4-17. Pipe
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Functional Timing Figure 4-19. Non-
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Functional Timing The TI486DLC/E sa
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Functional Timing 4.2.9 Hold Acknow
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Functional Timing 4.2.10 Coprocesso
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Functional Timing 4.2.12 Power Mana
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Functional Timing Stopping the Inpu
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Electrical Specifications 5-1
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Chapter 5 Electrical Specifications
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ElectricalConnecnons It is recommen
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Recommended Operating Conditions 5.
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DC Electrical Characteristics Table
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AC Characteristics Figure 5-2. TI48
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AC Characteristics Table 5-9. AC Ch
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AC Characteristics Table 5-11. AC C
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____ AC Characteristics 5.5.3 RESET
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Mechanical Specifications 6-1
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Chapter 6 Mechanical Specifications
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Pin Assignments Table 6-1. TI486SLC
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Pin Assignments Figure 6-3. TI486DL
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Package Dimensions 6.2 Package Dime
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Thermal Characteristics 6.3 Thermal
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Instruction Set 7-1
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Chapter 7 Instruction Set This sect
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Instruction Fields 7.2 Instruction
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Instruction Fields 7.2.5 reg Field
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Instruction Fields Table 7-7. mod r
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Instruction Fields 7.2.11 sreg3 Fie
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Clock Count Summary 7.4 Clock Count
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--- --;.J -L 01 Table 7-17. Instruc
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I . ~ -.....J Table 7-17. Instructi
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Table 7-17. Instructions, Opcodes,
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-....J N (J.) Table 7-17. Instructi
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I I i I i Table 7-17. Instructions,
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...... ...... '" Table 7-17. Instru
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-....J N co Table 7-17. Instruction
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"-.I ~ Table 7-17. Instructions, Op
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U Appendix A TI486 SMM Pro rammer's
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SMM Implementation A.2 SMM Implemen
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Figure A-1. SMM Memory Space Header
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SMM Implementation 6) NMI is the on
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Instruction Summary A.4 Instruction
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Instruction Summary A.4.3 Resume No
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Instruction Summary A.4.6 Save LDTR
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8MI Handler Example A.5 SMI Handler
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8MI Handler Example execute_halt: C
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8MI Handler Example COMMENT A The T
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8MI Handler Example arrl arr2 arr3
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.MODEL SMALL . STACK .386P INCLUDE
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Testing/Debugging SMM Code sgdt COM
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Testing/Debugging SMM Code i*******
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TI486 Power Management Features A.7
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Detection of Tl486 CPU A.9 Detectio
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Detection of SMM Capable Version A.
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A.11 SMM Feature Comparison SMM Fea
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SMM Instruction Macros COMMENT A Co
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SMM Instruction Macros SMM Instruct
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A.14 Format of Data Used by SVDC/RS
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Altering SMM Code Limits A.1S Alter
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SMM Errata A.16 SMM Errata The foll
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Appendix B TI486 Cache Flush B.1 Ge
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Appendix C TI486 BIOS Modification
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Introduction Some example assembler
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Appendix D Ordering Information 0.1
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~TEXAS INSTRUMENTS Printed in U.S.A
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