AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exception Real Invalid-operation exception (IE) X SIMD Floating-Point Exceptions 92 CVTTPS2DQ Virtual 8086 Protected Cause of Exception X X A source operand was an SNaN value, a QNaN value, or ±infinity. X X X A source operand was too large to fit in the destination format. Precision exception (PE) X X X A result could not be represented exactly in the destination format.
26568—Rev. 3.05—September 2003 AMD64 Technology CVTTPS2PI Convert Packed Single-Precision Floating-Point to Packed Doubleword Integers, Truncated Converts two packed single-precision floating-point values in the low-order 64 bits of an XMM register or a 64-bit memory location to two packed 32-bit signed integer values and writes the converted values in an MMX register. Mnemonic Opcode Description CVTTPS2PI mmx, xmm/mem64 0F 2C /r Converts packed single-precision floating-point values in an XMM register or 64-bit memory location to doubleword integer values in the destination MMX register. Inexact results are truncated. If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If the floating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximum signed doubleword (–2 31 to +2 31 –1), the instruction returns the 32-bit indefinite integer value (8000_0000h) when the invalidoperation exception (IE) is masked. Related Instructions CVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTSS2SI rFLAGS Affected None mmx 63 32 31 0 xmm/mem64 127 64 63 32 31 0 convert convert cvttps2pi.eps CVTTPS2PI 93
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