AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exception Real Invalid-operation exception (IE) X SIMD Floating-Point Exceptions 48 CVTPD2DQ Virtual 8086 Protected Cause of Exception X X A source operand was an SNaN value, a QNaN value, or ±infinity. X X X A source operand was too large to fit in the destination format. Precision exception (PE) X X X A result could not be represented exactly in the destination format.
26568—Rev. 3.05—September 2003 AMD64 Technology CVTPD2PI Convert Packed Double-Precision Floating-Point to Packed Doubleword Integers Converts two packed double-precision floating-point values in an XMM register or a 128-bit memory location to two packed 32-bit signed integer values and writes the converted values in an MMX register. Mnemonic Opcode Description CVTPD2PI mmx, xmm2/mem128 66 0F 2D /r Converts packed double-precision floating-point values in an XMM register or 128-bit memory location to packed doubleword integers values in the destination MMX register. If the result of the conversion is an inexact value, the value is rounded as specified by the rounding control bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximum signed doubleword (–2 31 to +2 31 – 1), the instruction returns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) is masked. Related Instructions CVTDQ2PD, CVTPD2DQ, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI, CVTTSD2SI rFLAGS Affected None mmx 63 32 31 0 xmm/mem128 127 64 63 0 convert convert cvtpd2pi.eps CVTPD2PI 49
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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