AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVDQ2Q Move Quadword to Quadword Moves the low-order 64-bit value in an XMM register to a 64-bit MMX register. Mnemonic Opcode Description MOVDQ2Q mmx, xmm F2 0F D6 /r Moves low-order 64-bit value from an XMM register to the destination MMX register. Related Instructions MOVD, MOVDQA, MOVDQU, MOVQ, MOVQ2DQ rFLAGS Affected None MXCSR Flags Affected None mmx xmm 63 0 127 64 63 0 148 MOVDQ2Q copy movdq2q.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. General protection X The destination operand was in a non-writable segment. x87 floating-point exception pending, #MF X X X An exception was pending due to an x87 floating-point instruction. MOVDQ2Q 149
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