AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 PCMPEQW Packed Compare Equal Words Compares corresponding packed 16-bit values in the first and second source operands and writes the result of each comparison in the corresponding 16 bits of the destination (first source). For each pair of words, if the values are equal, the result is all 1s. If the values are not equal, the result is all 0s. The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PCMPEQW xmm1, xmm2/mem128 66 0F 75 /r Compares packed 16-bit values in an XMM register and an XMM register or 128-bit memory location. Related Instructions PCMPEQB, PCMPEQD, PCMPGTB, PCMPGTD, PCMPGTW rFLAGS Affected None MXCSR Flags Affected None xmm1 xmm2/mem128 . . . . . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . compare . . all 1s or 0s 240 PCMPEQW 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . compare all 1s or 0s pcmpeqw-128.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. PCMPEQW 241
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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