AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 PSLLDQ Packed Shift Left Logical Double Quadword Left-shifts the 128-bit (double quadword) value in an XMM register by the number of bytes specified in an immediate byte value. The low-order bytes that are emptied by the shift operation are cleared to 0. If the shift value is greater than 15, the destination XMM register is cleared to all 0s. Mnemonic Opcode Description PSLLDQ xmm, imm8 66 0F 73 /7 ib Left-shifts double quadword value in an XMM register by the amount specified in an immediate byte value. Related Instructions PSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW rFLAGS Affected None MXCSR Flags Affected None xmm imm8 127 0 shift left 288 PSLLDQ 7 0 pslldq.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. PSLLDQ 289
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