AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Real Invalid opcode, #UD X X 334 PUNPCKLBW Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction.
26568—Rev. 3.05—September 2003 AMD64 Technology PUNPCKLDQ Unpack and Interleave Low Doublewords Unpacks the low-order doublewords from the first and second source operands and packs them into interleaved doublewords in the destination (first source). The highorder doublewords of the source operands are ignored. The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PUNPCKLDQ xmm1, xmm2/mem128 66 0F 62 /r Unpacks two low-order doublewords in an XMM register and another XMM register or 128-bit memory location and packs them into interleaved doublewords in the destination XMM register. 127 64 63 32 31 0 If the second source operand is all 0s, the destination contains the doubleword(s) from the first source operand zero-extended to 64 bits. This operation is useful for expanding unsigned 32-bit values to unsigned 64-bit operands for subsequent processing that requires higher precision. Related Instructions xmm1 xmm2/mem128 copy 127 96 95 64 63 32 31 0 127 64 63 32 31 0 copy copy copy punpckldq-128.eps PUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLQDQ, PUNPCKLWD PUNPCKLDQ 335
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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