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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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<strong>AMD</strong><strong>64</strong> Technology 26568—Rev. 3.05—September 2003<br />

.<br />

Mnemonic Opcode Description<br />

FXRSTOR mem512env 0F AE /1 Restores XMM, MM, and x87 state from 512-byte memory<br />

location.<br />

Related Instructions<br />

FWAIT, FXSAVE<br />

rFLAGS Affected<br />

None<br />

MXCSR Flags Affected<br />

FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE<br />

M M M M M M M M M M M M M M M M<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Note:<br />

A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank.<br />

Exceptions<br />

Exception Real<br />

Invalid opcode, #UD X<br />

114 FXRSTOR<br />

Virtual<br />

8086 Protected Cause of Exception<br />

X<br />

X X X The emulate bit (EM) of CR0 was set to 1.<br />

Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1.<br />

X<br />

The FXSAVE/FXRSTOR instructions are not supported, as<br />

indicated by bit 24 of CPUID standard funcion 1 or<br />

extended function 8000_0001h.

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