AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 UNPCKLPS Unpack Low Single-Precision Floating-Point Unpacks the low-order single-precision floating-point values in the first and second source operands and packs them into interleaved doublewords in the destination (first source). The high-order quadwords of the source operands are ignored. The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location Mnemonic Opcode Description UNPCKLPS xmm1, xmm2/mem128 0F 14 /r Unpacks low-order single-precision floating-point values in an XMM register and another XMM register or 128-bit memory location and packs them into the destination XMM register. Related Instructions UNPCKHPD, UNPCKHPS, UNPCKLPD rFLAGS Affected None MXCSR Flags Affected None xmm1 xmm2/mem128 127 64 63 32 31 0 copy 127 96 95 64 63 32 31 0 394 UNPCKLPS 127 64 63 32 31 0 copy copy copy unpcklps.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. UNPCKLPS 395
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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