AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 XORPD Logical Bitwise Exclusive OR Packed Double-Precision Floating-Point Performs a bitwise logical Exclusive OR of the two packed double-precision floatingpoint values in the first source operand and the corresponding two packed doubleprecision floating-point values in the second source operand and writes the result in the destination (first source). The first source/destination operand is an XMM register. The second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description XORPD xmm1, xmm2/mem128 66 0F 57 /r Performs bitwise logical XOR of two packed double-precision floating-point values in an XMM register and in another XMM register or 128-bit memory location and writes the result in the destination XMM register. Related Instructions ANDNPD, ANDNPS, ANDPD, ANDPS, ORPD, ORPS, XORPS rFLAGS Affected None MXCSR Flags Affected None 127 64 63 0 127 64 63 0 XOR xmm1 xmm2/mem128 XOR 396 XORPD xorpd.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction. XORPD 397
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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