AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exceptions Exception Real Invalid opcode, #UD X 266 PMULHUW Virtual 8086 Protected Cause of Exception X X The SSE instructions are not supported, as indicated by bit 25 in CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. X X X Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. X X X The memory operand was not aligned on a 16-byte boundary. Page fault, #PF X X A page fault resulted from the execution of the instruction.
26568—Rev. 3.05—September 2003 AMD64 Technology PMULHW Packed Multiply High Signed Word Multiplies each packed 16-bit signed integer value in the first source operand by the corresponding packed 16-bit signed integer in the second source operand and writes the high-order 16 bits of the intermediate 32-bit result of each multiplication in the corresponding word of the destination (first source). The first source/destination operand is an XMM register and the second source operand is another XMM register or 128-bit memory location. Mnemonic Opcode Description PMULHW xmm1, xmm2/mem128 66 0F E5 /r Multiplies packed 16-bit signed integer values in an XMM register and another XMM register or 128-bit memory location and writes the high-order 16 bits of each result in the destination XMM register. Related Instructions PMADDWD, PMULHUW, PMULLW, PMULUDQ rFLAGS Affected None MXCSR Flags Affected None multiply xmm1 xmm2/mem128 . . . . . . 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . multiply 127 112 111 96 95 80 79 64 63 48 47 32 31 16 15 0 . . . . . . pmulhw-128.eps PMULHW 267
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