AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

26568—Rev. 3.05—September 2003 AMD64 Technology
Exceptions
Exception Real
Invalid opcode, #UD X
X
X
Virtual
8086 Protected Cause of Exception
X
X
X
X
X
X
The SSE2 instructions are not supported, as indicated by bit
26 of CPUID standard function 1.
The emulate bit (EM) of CR0 was set to 1.
The operating-system FXSAVE/FXRSTOR support bit
(OSFXSR) of CR4 was cleared to 0.
X X X There was an unmasked SIMD floating-point exception
while CR4.OSXMMEXCPT = 0.
See SIMD Floating-Point Exceptions, below, for details.
Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1.
Stack, #SS X X X A memory address exceeded the stack segment limit or was
non-canonical.
General protection, #GP X X X
A memory address exceeded a data segment limit or was
non-canonical.
X A null data segment was used to reference memory.
Page fault, #PF X X A page fault resulted from the execution of the instruction.
Alignment check, #AC X X An unaligned memory reference was performed while
alignment checking was enabled.
SIMD Floating-Point X X X There was an unmasked SIMD floating-point exception
Exception, #XF
while CR4.OSXMMEXCPT = 1.
See SIMD Floating-Point Exceptions, below, for details.
SIMD Floating-Point Exceptions
Invalid-operation
exception (IE)
X X X A source operand was an SNaN value.
X X X +infinity was added to -infinity.
Denormalized-operand
exception (DE)
X X X A source operand was a denormal value.
Overflow exception (OE) X X X A rounded result was too large to fit into the format of the
destination operand.
Underflow exception (UE) X X X A rounded result was too small to fit into the format of the
destination operand.
Precision exception (PE) X X X A result could not be represented exactly in the destination
format.
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