AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 CVTPS2PI Convert Packed Single-Precision Floating-Point to Packed Doubleword Integers Converts two packed single-precision floating-point values in the low-order 64 bits of an XMM register or a 64-bit memory location to two packed 32-bit signed integers and writes the converted values in an MMX register. Mnemonic Opcode Description CVTPS2PI mmx, xmm/mem64 0F 2D /r Converts packed single-precision floating-point values in an XMM register or 64-bit memory location to packed doubleword integers in the destination MMX register. If the result of the conversion is an inexact value, the value is rounded as specified by the rounding control bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximum signed doubleword (–2 31 to +2 31 – 1), the instruction returns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) is masked. Related Instructions CVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI, CVTTSS2SI rFLAGS Affected None mmx 63 32 31 0 64 CVTPS2PI xmm/mem64 127 64 63 32 31 0 convert convert cvtps2pi.eps
26568—Rev. 3.05—September 2003 AMD64 Technology MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE Exceptions M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank. Exception Real Invalid opcode, #UD X X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. x87 floating-point X X X An exception was pending due to an x87 floating-point exception pending, #MF instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point X X X There was an unmasked SIMD floating-point exception Exception, #XF while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. CVTPS2PI 65
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