AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

AMD64 Technology 26568—Rev. 3.05—September 2003
CMPSD Compare Scalar Double-Precision
Floating-Point
Compares the double-precision floating-point value in the low-order 64 bits of the first
source operand with the double-precision floating-point value in the low-order 64 bits
of the second source operand and writes the result in the low-order 64 bits of the
destination (first source). The type of comparison is specified by the three low-order
bits of the immediate-byte operand, as shown in Table 1-1 on page 24. The result of the
compare is a 64-bit value of all 1s (TRUE) or all 0s (FALSE). The first
source/destination operand is an XMM register. The second source operand is another
XMM register or 64-bit memory location. The high-order 64 bits of the destination
XMM register are not modified.
Mnemonic Opcode Description
CMPSD xmm1, xmm2/mem64, imm8 F2 0F C2 /r ib Compares double-precision floating-point values in
an XMM register and an XMM register or 64-bit
memory location.
xmm1 xmm2/mem64
127 64 63 0 127 64
63 0
imm8
7 0
compare
all 1s or 0s
Some compare operations that are not directly supported by the immediate-byte
encodings can be implemented by swapping the contents of the source and
destination operands and then executing the appropriate compare instruction using
the swapped values. These additional compare operations are shown in Table 1-1 on
page 24. When swapping operands, the first source XMM register is overwritten by the
result.
30 CMPSD
cmpsd.eps