AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVMSKPD Extract Packed Double-Precision Floating-Point Sign Mask Moves the sign bits of two packed double-precision floating-point values in an XMM register to the two low-order bits of a 32-bit general-purpose register, with zeroextension. Mnemonic Opcode Description MOVMSKPD reg32, xmm 66 0F 50 /r Move sign bits in an XMM register to a 32-bit general-purpose register. Related Instructions MOVMSKPS, PMOVMSKB rFLAGS Affected None MXCSR Flags Affected None 31 reg32 xmm 166 MOVMSKPD 0 1 0 127 63 0 copy sign copy sign movmskpd.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception (vector) Real Invalid opcode, #UD X Device not available, #NM X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1. MOVMSKPD 167
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