AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 Exception Real Invalid-operation exception (IE) Denormalized-operand exception (DE) SIMD Floating-Point Exceptions X X X A source operand was an SNaN or QNaN value. X X X A source operand was a denormal value. 126 MAXPS Virtual 8086 Protected Cause of Exception
26568—Rev. 3.05—September 2003 AMD64 Technology MAXSD Maximum Scalar Double-Precision Floating- Point Compares the double-precision floating-point value in the low-order 64 bits of the first source operand with the double-precision floating-point value in the low-order 64 bits of the second source operand and writes the numerically greater of the two values in the low-order quadword of the destination (first source). The first source/destination operand is an XMM register. The second source operand is another XMM register or a 64-bit memory location. The high-order quadword of the destination XMM register is not modified. Mnemonic Opcode Description MAXSD xmm1, xmm2/mem64 F2 0F 5F /r Compares scalar double-precision values in an XMM register and another XMM register or 64-bit memory location and writes the greater of the two values in the destination XMM register. If both source operands are equal to zero, the value in the second source operand is returned. If either operand is a NaN (SNaN or QNaN), and invalid-operation exceptions are masked, the second source operand is written to the destination. Related Instructions MAXPD, MAXPS, MAXSS, MINPD, MINPS, MINSD, MINSS rFLAGS Affected None xmm1 xmm2/mem64 127 64 63 0 127 64 63 0 maximum maxsd.eps MAXSD 127
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