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AMD64 Technology 26568—Rev. 3.05—September 2003 CVTSD2SS Convert Scalar Double-Precision Floating-Point to Scalar Single-Precision Floating-Point Converts a scalar double-precision floating-point value in the low-order 64 bits of an XMM register or a 64-bit memory location to a single-precision floating-point value and writes the converted value in the low-order 32 bits of another XMM register. The three high-order doublewords in the destination XMM register are not modified. If the result of the conversion is an inexact value, the value is rounded as specified by the rounding control bits (RC) in the MXCSR register. Mnemonic Opcode Description CVTSD2SS xmm1, xmm2/mem64 F2 0F 5A /r Converts a scalar double-precision floating-point value in an XMM register or 64-bit memory location to a scalar singleprecision floating-point value in the destination XMM register. Related Instructions CVTPD2PS, CVTPS2PD, CVTSS2SD rFLAGS Affected None xmm1 xmm2/mem64 127 32 31 0 70 CVTSD2SS 127 64 63 0 convert cvtsd2ss.eps
26568—Rev. 3.05—September 2003 AMD64 Technology MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE Exceptions M M M M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank. Exception Real Invalid opcode, #UD X X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point X X X There was an unmasked SIMD floating-point exception Exception, #XF while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions Invalid-operation exception (IE) X X X A source operand was an SNaN value. Overflow exception (OE) X X X A rounded result was too large to fit into the format of the destination operand. CVTSD2SS 71
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