AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...
AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...
AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
26568—Rev. 3.05—September 2003 <strong>AMD</strong><strong>64</strong> Technology<br />
Index<br />
Numerics<br />
16-bit mode.................................................. xv<br />
32-bit mode.................................................. xv<br />
<strong>64</strong>-bit mode..................................................<br />
A<br />
xv<br />
ADDPD .......................................................... 4<br />
ADDPS........................................................... 7<br />
addressing, RIP-relative............................ xxi<br />
ADDSD ........................................................ 10<br />
ADDSS ......................................................... 12<br />
ANDNPD ..................................................... 15<br />
ANDNPS ...................................................... 17<br />
ANDPD ........................................................ 19<br />
ANDPS.........................................................<br />
B<br />
21<br />
biased exponent..........................................<br />
C<br />
xv<br />
CMPPD ........................................................ 23<br />
CMPPS......................................................... 27<br />
CMPSD ........................................................ 30<br />
CMPSS ......................................................... 33<br />
COMISD....................................................... 36<br />
COMISS ....................................................... 39<br />
commit ........................................................ xvi<br />
compatibility mode..................................... xv<br />
CVTDQ2PD ................................................. 42<br />
CVTDQ2PS.................................................. 44<br />
CVTPD2DQ ................................................. 46<br />
CVTPD2PI ................................................... 49<br />
CVTPD2PS .................................................. 52<br />
CVTPI2PD ................................................... 55<br />
CVTPI2PS.................................................... 57<br />
CVTPS2DQ.................................................. 59<br />
CVTPS2PD .................................................. 62<br />
CVTPS2PI.................................................... <strong>64</strong><br />
CVTSD2SI ................................................... 67<br />
CVTSD2SS................................................... 70<br />
CVTSI2SD ................................................... 73<br />
CVTSI2SS .................................................... 76<br />
CVTSS2SD................................................... 79<br />
CVTSS2SI .................................................... 81<br />
CVTTPD2DQ............................................... 84<br />
CVTTPD2PI................................................. 87<br />
CVTTPS2DQ ............................................... 90<br />
CVTTPS2PI ................................................. 93<br />
CVTTSD2SI ................................................. 96<br />
CVTTSS2SI .................................................<br />
D<br />
99<br />
direct referencing...................................... xvi<br />
displacements............................................ xvi<br />
DIVPD ....................................................... 102<br />
DIVPS........................................................ 105<br />
DIVSD ....................................................... 108<br />
DIVSS ........................................................ 110<br />
double quadword....................................... xvi<br />
doubleword ................................................<br />
E<br />
xvi<br />
eAX–eSP register ..................................... xxii<br />
effective address size............................... xvii<br />
effective operand size.............................. xvii<br />
eFLAGS register...................................... xxiii<br />
eIP register .............................................. xxiii<br />
element ..................................................... xvii<br />
endian order ............................................. xxv<br />
exception................................................... xvii<br />
exponent .....................................................<br />
F<br />
xv<br />
flush........................................................... xvii<br />
FXRSTOR ................................................. 113<br />
FXSAVE ....................................................<br />
I<br />
116<br />
IGN ........................................................... xviii<br />
indirect.....................................................<br />
instructions<br />
xviii<br />
<strong>128</strong>-bit media ............................................. 1<br />
SSE ............................................................. 1<br />
SSE-2 .......................................................... 1<br />
L<br />
LDMXCSR ................................................ 118<br />
legacy mode ............................................. xviii<br />
legacy <strong>x86</strong> ................................................ xviii<br />
long mode................................................. xviii<br />
LSB ........................................................... xviii<br />
lsb .............................................................<br />
M<br />
xviii<br />
mask ........................................................... xix<br />
MASKMOVDQU ....................................... 120<br />
MAXPD ..................................................... 122<br />
MAXPS...................................................... 124<br />
MAXSD ..................................................... 127<br />
MAXSS ...................................................... 129<br />
Index 401