AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 All operations are "copy" xmm 127 64 63 0 0 xmm 127 32 31 0 0 63 0 146 MOVD with REX prefix reg/mem32 xmm 31 0 reg/mem64 xmm 63 32 31 0 0 mmx mmx 63 0 with REX prefix reg/mem64 reg/mem32 63 0 127 32 31 0 127 64 63 0 31 reg/mem64 reg/mem64 mmx 63 0 with REX prefix reg/mem32 mmx 31 0 with REX prefix reg/mem32 31 63 0 63 32 31 0 63 0 0 0 movd.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Related Instructions MOVDQA, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQ rFLAGS Affected None MXCSR Flags Affected None Exceptions (All Modes) Exception Real Invalid opcode, #UD X X X Virtual 8086 Protected Description X X X X X X The MMX instructions are not supported, as indicated by bit 23 of CPUID standard function 1. The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The instruction used XMM registers while CR4.OSFXSR=0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. Page fault, #PF X X A page fault resulted from the execution of the instruction. x87 floating-point exception pending, #MF X X X An x87 floating-point exception was pending and the instruction referenced an MMX register. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. MOVD 147
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