AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVQ2DQ Move Quadword to Quadword Moves a 64-bit value from an MMX register to the low-order 64 bits of an XMM register, with zero-extension to 128 bits. Mnemonic Opcode Description MOVQ2DQ xmm, mmx F3 0F D6 /r Moves 64-bit value from an MMX register to an XMM register. Related Instructions MOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQ rFLAGS Affected None MXCSR Flags Affected None 127 64 63 0 0 xmm mmx 178 MOVQ2DQ 63 0 copy movq2dq.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X Device not available, #NM x87 floating-point exception pending, #MF X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1. X X X An exception was pending due to an x87 floating-point instruction. MOVQ2DQ 179
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