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AMD64 Technology 26568—Rev. 3.05—September 2003 SUBSD Subtract Scalar Double-Precision Floating-Point Subtracts the double-precision floating-point value in the low-order quadword of the second source operand from the double-precision floating-point value in the low-order quadword of the first source operand and writes the result in the low-order quadword of the destination (first source). The high-order quadword of the destination is not modified. The first source/destination operand is an XMM register. The second source operand is another XMM register or 64-bit memory location. Mnemonic Opcode Description SUBSD xmm1, xmm2/mem64 F2 0F 5C /r Subtracts low-order double-precision floating-point value in an XMM register or in a 64-bit memory location from low-order double-precision floating-point value in another XMM register and writes the result in the destination XMM register. Related Instructions SUBPD, SUBPS, SUBSS rFLAGS Affected None xmm1 xmm2/mem64 127 64 63 0 127 64 63 0 subtract 376 SUBSD subsd.eps
26568—Rev. 3.05—September 2003 AMD64 Technology MXCSR Flags Affected FZ RC PM UM OM ZM DM IM DAZ PE UE OE ZE DE IE Exceptions M M M M M 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: A flag that may be set to one or cleared to zero is M (modified). Unaffected flags are blank. Exception Real Invalid opcode, #UD X X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE2 instructions are not supported, as indicated by bit 26 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X There was an unmasked SIMD floating-point exception while CR4.OSXMMEXCPT = 0. See SIMD Floating-Point Exceptions, below, for details. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X A memory address exceeded a data segment limit or was non-canonical. X A null data segment was used to reference memory. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. SIMD Floating-Point X X X There was an unmasked SIMD floating-point exception Exception, #XF while CR4.OSXMMEXCPT = 1. See SIMD Floating-Point Exceptions, below, for details. SIMD Floating-Point Exceptions Invalid-operation exception (IE) X X X A source operand was an SNaN value. X X X +infinity was subtracted from +infinity. X X X -infinity was subtracted from -infinity. SUBSD 377
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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