AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVHPS Move High Packed Single-Precision Floating-Point Moves two packed single-precision floating-point values: � from a 64-bit memory location to the high-order 64 bits of an XMM register, or � from the high-order 64 bits of an XMM register to a 64-bit memory location. The low-order 64 bits of the destination XMM register are not modified. Mnemonic Opcode Description MOVHPS xmm, mem64 0F 16 /r Moves two packed single-precision floating-point values from a 64-bit memory location to an XMM register. MOVHPS mem64, xmm 0F 17 /r Moves two packed single-precision floating-point values from an XMM register to a 64-bit memory location. 127 96 95 64 63 0 Related Instructions xmm mem64 mem64 MOVAPS, MOVHLPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPS 158 MOVHPS copy copy 63 32 31 0 xmm copy copy 63 32 31 0 127 96 95 64 63 0 movhps.eps
26568—Rev. 3.05—September 2003 AMD64 Technology rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Real Invalid opcode, #UD X X Virtual 8086 Protected Cause of Exception X X X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical. General protection, #GP X X X X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. MOVHPS 159
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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