AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

AMD64 Technology 26568—Rev. 3.05—September 2003
MOVNTPS Move Non-Temporal Packed
Single-Precision Floating-Point
Stores four single-precision floating-point XMM register values into a 128-bit memory
location. This instruction indicates to the processor that the data is non-temporal, and
is unlikely to be used again soon. The processor treats the store as a write-combining
(WC) memory write, which minimizes cache pollution. The exact method by which
cache pollution is minimized depends on the hardware implementation of the
instruction. For further information, see “Memory Optimization” in Volume 1.
Mnemonic Opcode Description
MOVNTPS mem128, xmm 0F 2B /r Stores four packed single-precision floating-point XMM register values
into a 128-bit memory location, minimizing cache pollution.
MOVNTPD is weakly-ordered with respect to other instructions that operate on
memory. Software should use an SFENCE instruction to force strong memory ordering
of MOVNTPD with respect to other stores.
Related Instructions
MOVNTDQ, MOVNTI, MOVNTPD, MOVNTQ
rFLAGS Affected
None
mem128 xmm
127 96 95 64 63 32
31
0
174 MOVNTPS
127 96 95 64 63 32 31
0
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movntps.eps