AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 MOVLHPS Move Packed Single-Precision Floating-Point Low to High Moves two packed single-precision floating-point values from the low-order 64 bits of an XMM register to the high-order 64 bits of another XMM register. The low-order 64 bits of the destination XMM register are not modified. Mnemonic Opcode Description MOVLHPS xmm1, xmm2 0F 16 /r Moves two packed single-precision floating-point values from an XMM register to another XMM register. Related Instructions MOVAPS, MOVHLPS, MOVHPS, MOVLPS, MOVMSKPS, MOVSS, MOVUPS rFLAGS Affected None MXCSR Flags Affected None xmm1 xmm2 127 96 95 64 63 0 160 MOVLHPS 127 64 63 32 31 0 copy copy movlhps.eps
26568—Rev. 3.05—September 2003 AMD64 Technology Exceptions Exception Real Invalid opcode, #UD X Device not available, #NM X X Virtual 8086 Protected Cause of Exception X X X X X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 was cleared to 0. X X X The task-switch bit (TS) of CR0 was set to 1. MOVLHPS 161
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