AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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AMD64 Technology 26568—Rev. 3.05—September 2003 STMXCSR Store MXCSR Control/Status Register Saves the contents of the MXCSR register in a 32-bit location in memory. The MXCSR register is described in “Registers” in Volume 1. Mnemonic Opcode Description STMXCSR mem32 0F AE /3 Stores contents of MXCSR in 32-bit memory location. Related Instructions LDMXCSR rFLAGS Affected None MXCSR Flags Affected None Exceptions Exception Real Invalid opcode, #UD X X 368 STMXCSR Virtual 8086 Protected Cause of Exception X X X X The SSE instructions are not supported, as indicated by bit 25 of CPUID standard function 1. The emulate bit (EM) of CR0 was set to 1. X X X The operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0. Device not available, #NM X X X The task-switch bit (TS) of CR0 was set to 1. Stack, #SS X X X A memory address exceeded the stack segment limit or was non-canonical.
26568—Rev. 3.05—September 2003 AMD64 Technology Exception Real General protection, #GP X X X Virtual 8086 Protected Cause of Exception X A memory address exceeded a data segment limit or was non-canonical. A null data segment was used to reference memory. X The destination operand was in a non-writable segment. Page fault, #PF X X A page fault resulted from the execution of the instruction. Alignment check, #AC X X An unaligned memory reference was performed while alignment checking was enabled. STMXCSR 369
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AMD x86-64 Architecture Programmer's Manual, Volume 4, 128-Bit ...

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